Philips Semiconductors
P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
Product data Rev. 03 — 15 December 2004 28 of 49
9397 750 14471
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.17.1 Mode 0
Putting either Timer into Mode 0 makes it look like an 8048 Timer, which is an 8-bit
Counter with a divide-by-32 prescaler. In this mode, the Timer register is configured
as a 13-bit register. Mode 0 operation is the same for Timer 0 and Timer 1.
8.17.2 Mode 1
Mode 1 is the same as Mode 0, except that all 16 bits of the timer register are used.
8.17.3 Mode 2
Mode 2 configures the Timer register as an 8-bit Counter with automatic reload.
Mode 2 operation is the same for Timer 0 and Timer 1.
8.17.4 Mode 3
When Timer 1 is in Mode 3 it is stopped. Timer 0 in Mode 3 forms two separate 8-bit
counters and is provided for applications that require an extra 8-bit timer. When
Timer 1 is in Mode 3 it can still be used by the serial port as a baud rate generator.
8.17.5 Mode 6
In this mode, the corresponding timer can be changed to a PWM with a full period of
256 timer clocks.
8.17.6 Timer overflow toggle output
Timers 0 and 1 can be configured to automatically toggle a port output whenever a
timer overflow occurs. The same device pins that are used for the T0 and T1 count
inputs are also used for the timer toggle outputs. The port outputs will be a logic 1
prior to the first timer overflow when this mode is turned on.
8.18 Real-Time clock/system timer
The P89LPC924/925 has a simple Real-Time clock that allows a user to continue
running an accurate timer while the rest of the device is powered-down. The
Real-Time clock can be a wake-up or an interrupt source. The Real-Time clock is a
23-bit down counter comprised of a 7-bit prescaler and a 16-bit loadable down
counter. When it reaches all ‘0’s, the counter will be reloaded again and the RTCF
flag will be set. The clock source for this counter can be either the CPU clock (CCLK)
or the XTAL oscillator, provided that the XTAL oscillator is not being used as the CPU
clock. If the XTAL oscillator is used as the CPU clock, then the RTC will use CCLK as
its clock source. Only power-on reset will reset the Real-Time clock and its
associated SFRs to the default state.
8.19 UART
The P89LPC924/925 has an enhanced UART that is compatible with the
conventional 80C51 UART except that Timer 2 overflow cannot be used as a baud
rate source. The P89LPC924/925 does include an independent Baud Rate
Generator. The baud rate can be selected from the oscillator (divided by a constant),
Timer 1 overflow, or the independent Baud Rate Generator. In addition to the baud
rate generation, enhancements over the standard 80C51 UART include Framing
Error detection, automatic address recognition, selectable double buffering and
several interrupt options. The UART can be operated in 4 modes: shift register, 8-bit
UART, 9-bit UART, and CPU clock/32 or CPU clock/16.
Philips Semiconductors
P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
Product data Rev. 03 — 15 December 2004 29 of 49
9397 750 14471
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.19.1 Mode 0
Serial data enters and exits through RxD. TxD outputs the shift clock. 8 bits are
transmitted or received, LSB first. The baud rate is fixed at
1
16
of the CPU clock
frequency.
8.19.2 Mode 1
10 bits are transmitted (through TxD) or received (through RxD): a start bit
(logical ‘0’), 8 data bits (LSB first), and a stop bit (logical ‘1’). When data is received,
the stop bit is stored in RB8 in Special Function Register SCON. The baud rate is
variable and is determined by the Timer 1 overflow rate or the Baud Rate Generator
(described in Section 8.19.5 “Baud rate generator and selection”).
8.19.3 Mode 2
11 bits are transmitted (through TxD) or received (through RxD): start bit (logical ‘0’),
8 data bits (LSB first), a programmable 9
th
data bit, and a stop bit (logical ‘1’). When
data is transmitted, the 9
th
data bit (TB8 in SCON) can be assigned the value of ‘0’ or
‘1’. Or, for example, the parity bit (P, in the PSW) could be moved into TB8. When
data is received, the 9
th
data bit goes into RB8 in Special Function Register SCON,
while the stop bit is not saved. The baud rate is programmable to either
1
16
or
1
32
of
the CPU clock frequency, as determined by the SMOD1 bit in PCON.
8.19.4 Mode 3
11 bits are transmitted (through TxD) or received (through RxD): a start bit
(logical ‘0’), 8 data bits (LSB first), a programmable 9
th
data bit, and a stop bit
(logical ‘1’). In fact, Mode 3 is the same as Mode 2 in all respects except baud rate.
The baud rate in Mode 3 is variable and is determined by the Timer 1 overflow rate or
the Baud Rate Generator (described in Section 8.19.5 “Baud rate generator and
selection”).
8.19.5 Baud rate generator and selection
The P89LPC924/925 enhanced UART has an independent Baud Rate Generator.
The baud rate is determined by a baud-rate preprogrammed into the BRGR1 and
BRGR0 SFRs which together form a 16-bit baud rate divisor value that works in a
similar manner as Timer 1 but is much more accurate. If the baud rate generator is
used, Timer 1 can be used for other timing functions.
The UART can use either Timer 1 or the baud rate generator output (see Figure 7).
Note that Timer T1 is further divided by 2 if the SMOD1 bit (PCON.7) is set. The
independent Baud Rate Generator uses OSCCLK.
Fig 7. Baud rate sources for UART (Modes 1, 3).
Baud Rate Modes 1 and 3
SBRGS = 1
SBRGS = 0
SMOD1 = 0
SMOD1 = 1
2
Timer 1 Overflow
(PCLK-based)
Baud Rate Generator
(CCLK-based)
002aaa419
Philips Semiconductors
P89LPC924/925
8-bit microcontrollers with accelerated two-clock 80C51 core
Product data Rev. 03 — 15 December 2004 30 of 49
9397 750 14471
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
8.19.6 Framing error
Framing error is reported in the status register (SSTAT). In addition, if SMOD0
(PCON.6) is ‘1’, framing errors can be made available in SCON.7 respectively. If
SMOD0 is ‘0’, SCON.7 is SM0. It is recommended that SM0 and SM1 (SCON.7:6)
are set up when SMOD0 is ‘0’.
8.19.7 Break detect
Break detect is reported in the status register (SSTAT). A break is detected when
11 consecutive bits are sensed LOW. The break detect can be used to reset the
device and force the device into ISP mode.
8.19.8 Double buffering
The UART has a transmit double buffer that allows buffering of the next character to
be written to SBUF while the first character is being transmitted. Double buffering
allows transmission of a string of characters with only one stop bit between any two
characters, as long as the next character is written between the start bit and the stop
bit of the previous character.
Double buffering can be disabled. If disabled (DBMOD, i.e., SSTAT. 7 = ‘0’), the UART
is compatible with the conventional 80C51 UART. If enabled, the UART allows writing
to SnBUF while the previous data is being shifted out. Double buffering is only
allowed in Modes 1, 2 and 3. When operated in Mode 0, double buffering must be
disabled (DBMOD = ‘0’).
8.19.9 Transmit interrupts with double buffering enabled (Modes 1, 2 and 3)
Unlike the conventional UART, in double buffering mode, the Tx interrupt is generated
when the double buffer is ready to receive new data.
8.19.10 The 9
th
bit (bit 8) in double buffering (Modes 1, 2 and 3)
If double buffering is disabled TB8 can be written before or after SBUF is written, as
long as TB8 is updated some time before that bit is shifted out. TB8 must not be
changed until the bit is shifted out, as indicated by the Tx interrupt.
If double buffering is enabled, TB8 must be updated before SBUF is written, as TB8
will be double-buffered together with SBUF data.

P89LPC925FN,129

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
IC MCU 8BIT 8KB FLASH 20DIP
Lifecycle:
New from this manufacturer.
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