Expand menu
Hello, Sign in
My Account
0
Cart
Home
Products
Sensors
Semiconductors
Passive Components
Connectors
Power
Electromechanical
Optoelectronics
Circuit Protection
Integrated Circuits - ICs
Main Products
Manufacturers
Blog
Services
About OMO
About Us
Contact Us
Check Stock
72615L50PF8
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P17
10
INDUSTRIAL TEMPERATURE RANGE
IDT72605/72615 CMOS SYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
t
CS
NO OPERATION
CLK
A
EN
A
CS
A
A
0
, A
1,
A
2
R/
W
A
EF
BA
D
A0-
D
A17
CLK
B
OE
A
t
CLK
t
CLKH
t
CLKL
t
CH
t
EF
t
A
t
OLZ
t
OE
t
OHZ
t
SKEW1
t
EF
NO WRITE
WRITE
VALID DATA
2704 drw 08
t
DS
DATA IN VALID
t
SKEW1
READ
NO READ OPERATION
CLK
B
EN
B
R/
W
B
FF
BA
D
B0-
D
B17
CLK
A
NO OPERATION
t
DH
t
FF
t
FF
t
CS
t
CH
t
CLKL
t
CLKH
t
CLK
2704 drw 09
Figure 6. Port B (B
→
→
→
→
→
A) Write Timing
Figure 5. Port A (B
→
→
→
→
→
A) Read Timing
11
IDT72605/72615 CMOS SYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
VALID DATA
t
SKEW1
NO WRITE OPERATION
CLK
B
EN
B
R/
W
B
EF
BA
D
B0-
D
B17
CLK
A
NO OPERATION
t
EF
t
EF
t
CS
t
CH
t
CLKL
t
CLKH
t
CLK
OE
B
t
A
WRITE
t
OE
t
OLZ
t
OHZ
2704 drw 10
(First Valid Write)
(1)
t
SKEW1
CLK
A
EN
B
R/
W
A
EF
AB
D
B0-
D
B17
CLK
B
t
EF
t
CS
OE
B
t
A
t
OE
t
OLZ
R/
W
B
D
A0-
D
A17
CS
A
,
EN
A
A
0
, A
1
, A
2
t
A
t
FRL
t
CS
D
0
D
1
D
1
D
2
D
3
D
0
t
DS
2704 drw 11
Figure 7. Port B (A
→
→
→
→
→
B) Read Timing
NOTE:
1
.
When
t
SKEW1
≥
minimum specification, t
FRL
(Max.) = t
CLK
+ t
SKEW1
t
SKEW1
< minimum specification, t
FRL
(Max.) = 2t
CLK
+ t
SKEW1 or
t
CLK
+
t
SKEW1
The Latency Timing applies only at the Empty Boundary (
EF
= LOW).
Figure 8. A
→
→
→
→
→
B First Data Word Latency after Reset for Simultaneous Read and Write
12
INDUSTRIAL TEMPERATURE RANGE
IDT72605/72615 CMOS SYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
(First valid write)
(1)
t
SKEW1
CLK
B
EN
B
R/
W
B
EF
BA
D
A0-
D
A17
CLK
A
t
EF
t
CS
OE
A
t
A
t
OE
t
OLZ
R/
W
A
D
B0-
D
B17
CS
A
,
EN
A
A
0
, A
1
, A
2
t
A
t
FRL
t
CS
D
0
D
1
D
1
D
2
D
3
D
0
t
DS
2704 drw 12
NOTE:
1
.
When
t
SKEW1
≥
minimum specification, t
FRL
(Max.) = t
CLK
+ t
SKEW1
t
SKEW1
< minimum specification, t
FRL
(Max.) = 2t
CLK
+ t
SKEW1
The Latency Timing apply only at the Empty Boundary (
EF
= LOW).
Figure 9. B
→
→
→
→
→
A First Data Word Latency after Reset for Simultaneous Read and Write
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P17
72615L50PF8
Mfr. #:
Buy 72615L50PF8
Manufacturer:
IDT
Description:
FIFO 512X18 BI-FIFO PARA/SYNCH
Lifecycle:
New from this manufacturer.
Delivery:
DHL
FedEx
Ups
TNT
EMS
Payment:
T/T
Paypal
Visa
MoneyGram
Western
Union
Products related to this Datasheet
72615L25PF
72615L50J
72615L50J8
72615L50PF8
72615L20PF8
72615L25J8
72615L25J
72615L20J8
72615L25PF8
72615L35J
72615L20PF
72615L35PF8
72615L35J8
72615L35PF
72615L50PF