15
IDT72605/72615 CMOS SYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2 INDUSTRIAL TEMPERATURE RANGE
(1)
WRITE
READ
n words in FIFO
n+1 words in FIFO
t
CLKL
2704 drw 15
CLK
A
EN
A
(R/W
A
= 0)
PAE
AB
CLK
B
EN
A
(R/W
B
= 1)
t
CLKH
t
CS
t
CH
t
SKEW2
t
PAE
t
CS
t
CH
t
PAE
(2)
WRITE
READ
(2)
Full - (m+1) words in FIFO
Full - m words in FIFO
tCLKL
2704 drw 16
CLKA
ENA
(R/WA = 0)
PAF
AB
CLKB
ENB
(R/WB = 1)
t
CLKH
tCS
tCH
tPAF
tCS
tCH
tPAF
NOTES:
1. tSKEW2 the minimum time between a rising CLKA edge and a rising CLKB edge for PAEAB to change during that clock cycle. If the time between the rising edge of CLKA and
the rising edge of CLKB is less than tSKEW, then PAEAB may not go HIGH until the next CLKB rising edge.
2. If a read is performed on this rising edge of the read clock, there will be Empty + (n + 1) words in the FIFO when PAE goes LOW.
Figure 12. A
→→
→→
→
B Programmable Almost-Empty Flag Timing
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAFAB to change during that clock cycle. If the time between the rising edge of CLKB
and the rising edge of CLKA is less than tSKEW2, then PAFAB may not go HIGH until the next CLKA rising edge.
2. If a write is performed on this rising edge of the write clock, there will be Full - (m + 1) words in the FIFO when PAF goes LOW.
Figure 13. A
→→
→→
→
B Programmable Almost-Full Flag Timing
