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72615L50PF8

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
16
INDUSTRIAL TEMPERATURE RANGE
IDT72605/72615 CMOS SYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
Full - m words in FIFO
WRITE
(2)
Full - (m+1) words in FIFO
tCLKL
2704 drw 18
CLKB
ENB
(R/WA = 0)
PAF
BA
CLKA
ENA
(R/WA = 1)
t
CLKH
tCS
tCH
tPAF
tCS
tCH
tSKEW2
(1)
tPAF
READ
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAFBA to change during that clock cycle. If the time between the rising edge of CLKB
and the rising edge of CLKA is less than tSKEW2, then PAFBA may not go HIGH until the next CLKA rising edge.
2. If a write is performed on this rising edge of the write clock, there will be Full - (m + 1) words in the FIFO when PAF goes LOW.
Figure 15. B
→→
→→
→
A Programmable Almost-Full Flag Timing
(1)
WRITE
READ
n words in FIFO
n+1 words in FIFO
t
CLKL
2704 drw 17
CLK
B
EN
B
(R/W
A
= 0)
PAE
BA
CLK
A
EN
A
(R/W
A
= 1)
t
CLKH
t
CS
t
CH
t
PAE
t
CS
t
CH
t
SKEW2
t
PAE
(2)
Figure 14. B
→→
→→
→
A Programmable Almost-Empty Flag Timing
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for PAEBA to change during that clock cycle. If the time between the rising edge of CLKB
and the rising edge of CLKA is less than tSKEW2, then PAEBA may not go HIGH until the next CLKA rising edge.
2. If a read is performed on this rising edge of the read clock, there will be Empty + (n - 1) words in the FIFO when PAE goes LOW.
17
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 408-360-1753
San Jose, CA 95138 fax: 408-284-2775 email: FIFOhelp@idt.com
www.idt.com
ORDERING INFORMATION
DATASHEET DOCUMENT HISTORY
11/02/2000 pgs. 1, 2, 3, 4, 16
04/08/2003 pg. 17.
02/08/2009 pgs. 1 and 17.
02/25/2013 pgs. 1, 7 and 17.
XXXXX
X
XX X X
Device Type Power Speed Package Process/
Temperature
Range
Blank
J
PF
20
25
35
50
L
72605
72615
Industrial (-40°C to +85°C)
Plastic Leaded Chip Carrier (PLCC, J68-1)
Thin Quad Flat Pack (TQFP, PN64-1)
Low Power
256 x 18 ⎯ Parallel SyncBiFIFO
512 x 18 ⎯ Parallel SyncBiFIFO
2704 drw19
Clock Cycle Time (tCLK)
in Nanoseconds
Blank
8
Tube or Tray
Tape and Reel
X
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

72615L50PF8

Mfr. #:
Buy 72615L50PF8
Manufacturer:
IDT
Description:
FIFO 512X18 BI-FIFO PARA/SYNCH
Lifecycle:
New from this manufacturer.
Delivery:
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