7
IDT72605/72615 CMOS SYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2 INDUSTRIAL TEMPERATURE RANGE
Data A
CS
A R/WA ENA OEA I/O Port A Operation
0 0 0 0 I Data A is written on CLKA ↑. This write cycle immediately following low-impedance cycle is prohibited. Note
that even though OE
A = 0, a LOW logic level on R/WA, once qualified by a rising edge on CLKA, will put Data A into
a high-impedance state.
0 0 0 1 I Data A is written on CLKA ↑
0 0 1 X I Data A is ignored
0 1 0 0 O Data is read
(1)
from RAM array to output register on CLKA ↑, Data A is low-impedance
0 1 0 1 O Data is read
(1)
from RAM array to output register on CLKA ↑, Data A is high-impedance
0 1 1 0 O Output register does not change
(2)
, Data A is low-impedance
0 1 1 1 O Output register does not change
(2)
, Data A is high-impedance
1 0 X X I Data A is ignored
(3)
1 1 X X O Data A is high-impedance
(3)
NOTES:
1. When A2A1A0 = 000, the next B→A FIFO value is read out of the output register and the read pointer advances. If A2A1A0 = 001, the bypass path is selected and bypass
data from the Port B input register is read from the Port A output register. If A2A1A00 = 1XX, a flag offset register is selected and its offset is read out through Port A output
register.
2. Regardless of the condition of A2A1A0, the data in the Port A output register does not change and the B→A read pointer does not advance.
3. If CSA# is HIGH, then BYPB is HIGH. No bypass occur under this condition.
TABLE 1 ⎯ PORT A OPERATION CONTROL SIGNALS
CSA A2 A1 A0 Read Write
0000 B→A FIFO A→B FIFO
0001 18-bit Bypass Path
0100 A→B FIFO Almost-Empty
Flag Offset
0101 A→B FIFO Almost-Full
Flag Offset
0110 B→A FIFO Almost-Empty
Flag Offset
0111 B→A FIFO Almost-Full
Flag Offset
1 X X X Port A Disabled
TABLE 2 ⎯ ACCESSING PORT A RE-
SOURCES USING CSA, A2, A1, AND A0
of each port operate independently, Port A can be reading bypass data at the
same time Port B is reading bypass data.
When R/WA and ENA is LOW, data on pins DA0-DA17 is written into Port
A input register. Following the rising edge of CLKA for this write, the A→B Full
Flag (FFAB) goes LOW. Subsequent writes into Port A are blocked by internal
logic until FFAB goes HIGH again. On the next CLKB rising edge, the A→B
Empty Flag (EFAB) goes HIGH indicating to Port B that data is available. Once
R/WB is HIGH and ENB is LOW, data is read into the Port B output register. OEB
still controls whether Port B is in a high-impedance state. When OEB is LOW,
the output register data appears at DB0-DB17. EFAB goes LOW following the
CLKB rising edge for this read. FFAB goes HIGH on the next CLKA rising edge,
letting Port A know that another word can be written through the bypass path.
Bypass data transfers from Port B to Port A work in a similar manner with
EFBA and FFBA indicating the Port A output register state.
When the Port A address changes from bypass mode (A2A1A0=001) to
FIFO mode (A2A1A0=000) on the rising edge of CLKA, the data held in the Port
B output register may be overwritten. Unless Port A monitors the BYPB pin and
waits for Port B to clock out the last bypass word, data from the A→B FIFO will
overwrite data in the Port B output register. BYPB will go HIGH on the rising
edge of CLKB signifying that Port B has finished its last bypass operation. Port
B must read any bypass data in the output register on this last CLKB clock or
it is lost and the SyncBiFIFO returns to FIFO operations. It is especially important
to monitor BYPB when CLKB is much slower than CLKA to avoid this condition.
BYPB will also go HIGH after CSA is brought HIGH; in this manner the Port B
bypass data may also be lost.
Since the Port A processor controls CSA and the bypass mode, this scenario
can be handled for B→A bypass data. The Port A processor must be set up
to read the last bypass word before leaving bypass mode.
PORT A CONTROL SIGNALS
The Port A control signals pins dictate the various operations shown in Table
2. Port A is accessed when CSA is LOW, and is inactive if CSA is HIGH. R/
WA and ENA lines determine when Data A can be written or read. If R/WA and
ENA are LOW, data is written into input register on the LOW-to-HIGH transition
of CLKA. If R/WA is HIGH and OEA is LOW, data comes out of bus and is read
from output register into three-state buffer. Refer to pin descriptions for more
information.
PROGRAMMABLE FLAGS
The IDT SyncBiFIFO has eight flags: four flags for A→B FIFO (EFAB,
PAEAB, PAFAB, FFAB), and four flags for B→A FIFO (EFBA, PAEBA, PAFBA,
FFBA). The Empty and Full flags are fixed, while the Almost-Empty and Almost-
Full offsets can be set to any depth through the Flag Offset Registers (see Table
3). The flags are asserted at the depths shown in the Flag Truth Table (Table
4). After reset, the programmable flag offsets are set to 8. This means the Almost-
Empty flags are asserted at Empty +8 words deep, and the Almost-Full flags are
asserted at Full -8 words deep.
The PAEAB is synchronized to CLKB, while PAEAB is synchronized to CLKA;
and PAEBA is synchronized to CLKA, while PAEBA is synchronized to CLKB.
If the minimum time (tSKEW2) between a rising CLKB and a rising CLKA is met,
the flag will change state on the current clock; otherwise, the flag may not change
state until the next clock rising edge. For the specific flag timings, refer to Figures
12-15.
PORT B CONTROL SIGNALS
The Port B control signal pins dictate the various operations shown in Table
5. Port B is independent of CSA. R/WB and ENB lines determine when Data
