1
DATASHEET
High Speed, Dual Channel, 6A, Power MOSFET Driver
with Enable Inputs
ISL89163, ISL89164, ISL89165
The ISL89163, ISL89164, and ISL89165 are high-speed, 6A,
dual channel MOSFET drivers with enable inputs. These parts are
very similar to the ISL89160, ISL89161, ISL89162 drivers but
with an added enable input for each channel occupying NC pins 1
and 8 of the ISL89160, ISL89161, ISL89162.
Precision thresholds on all logic inputs allow the use of external
RC circuits to generate accurate and stable time delays on both
the main channel inputs, INA and INB, and the enable inputs,
ENA and ENB. The precision delays capable of these precise logic
thresholds makes these parts very useful for dead-time control
and synchronous rectifiers. Note that the ENable and INput logic
inputs can be interchanged for alternate logic implementations.
Three input logic thresholds are available: 3.3V (CMOS), 5.0V
(CMOS or TTL compatible), and CMOS thresholds that are
proportional to VDD.
At high switching frequencies, these MOSFET drivers use very
little internal bias currents. Separate, non-overlapping drive
circuits are used to drive each CMOS output FET to prevent
shoot-through currents in the output stage.
The start-up sequence is designed to prevent unexpected glitches
when V
DD
is being turned on or turned off. When V
DD
< ~1V, an
internal 10kΩ resistor between the output and ground helps to
keep the output voltage low. When ~1V < V
DD
< UV, both outputs
are driven low with very low resistance and the logic inputs are
ignored. This insures that the driven FETs are off. When
V
DD
> UVLO, and after a short delay, the outputs now respond to
the logic inputs.
Features
Dual output, 6A peak currents, can be paralleled
Dual AND-ed input logic, (INput and ENable)
•Typical ON-resistance <1Ω
Specified Miller plateau drive currents
Very low thermal impedance (
JC
= 3°C/W)
Hysteretic Input logic levels for 3.3V CMOS, 5V CMOS, TTL, and
Logic levels proportional to V
DD
Precision threshold inputs for time delays with external RC
components
20ns rise and fall time driving a 10nF load.
Applications
Synchronous Rectifier (SR) driver
Switch mode power supplies
Motor drives, Class D amplifiers, UPS, inverters
Pulse transformer driver
Clock/line driver
Related Literature
For a full list of related documents, visit our web page
ISL89163
, ISL89164, ISL89165 product pages
FIGURE 1. TYPICAL APPLICATION
FIGURE 2. TEMP STABLE LOGIC THRESHOLDS
8
6
7
1
4
3
2
5
EPAD
V
DD
4.7µF
ENB
ENA
INA
INB
GND
OUTA
OUTB
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-40 -25 -10 5 20 35 50 65 80 95 110 125
OPTION B THRESHOLDS (5.0V)
TEMPERATURE (°C)
NEGATIVE THRESHOLD LIMITS
POSITIVE THRESHOLD LIMITS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC. 2010-2012, 2015, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
October 13, 2016
FN7707.5
ISL89163, ISL89164, ISL89165
2
FN7707.5
October 13, 2016
Submit Document Feedback
Block Diagram
OUTx
VDD
INx
GND
FOR CLARITY, ONLY ONE
CHANNEL IS SHOWN
EPAD
FOR PROPER THERMAL AND ELECTRICAL
PERFORMANCE, THE EPAD MUST BE
CONNECTED TO THE PCB GROUND PLANE.
SEPARATE FET DRIVES, WITH NON-
OVERLAPPING OUTPUTS, PREVENT
SHOOT-THRU CURRENTS IN THE OUTPUT
CMOS FETS RESULTING WITH VERY LOW
HIGH FREQUENCY OPERATING
CURRENTS.
ISL89164, ISL89165
ISL89163
10k
ENx
ENX AND INX INPUTS ARE
IDENTICAL AND MAY BE
INTERCHANGED FOR
ALTERNATE LOGIC
FOR OPTIONS A AND B, THE UV
COMPARATOR HOLDS OFF THE
OUTPUTS UNTIL VDD ~> 3.3VDC.
FOR OPTION C, THE UV
RELEASE IS ~> 6.5V
FIGURE 3. BLOCK DIAGRAM
Pin Configurations
ISL89163FR, ISL89163FB
(8 LD TDFN, EPSOIC)
TOP VIEW
ISL89164FR, ISL89164FB
(8 LD TDFN, EPSOIC)
TOP VIEW
ISL89165FR, ISL89165FB
(8 LD TDFN, EPSOIC)
TOP VIEW
1ENA
2INA
4INB
3GND
8ENB
7OUTA
6VDD
5OUTB
1ENA
2/INA
4/INB
3GND
8ENB
7OUTA
6VDD
5OUTB
1ENA
2/INA
4INB
3GND
8ENB
7OUTA
6VDD
5OUTB
Pin Descriptions
PIN
NUMBER SYMBOL
DESCRIPTION
(SEE TRUTH TABLE FOR
LOGIC POLARITIES)
1 ENA Channel A enable, 0V to VDD
2 INA, /INA Channel A input, 0V to VDD
3 GND Power Ground, 0V
4 INB, /INB Channel B enable, 0V to VDD
5OUTBChannel B output
6 VDD Power input, 4.5V to 16V
7 OUTA Channel A output, 0V to VDD
8 ENB Channel B enable, 0V to VDD
EPAD Power Ground, 0V
ISL89163, ISL89164, ISL89165
3
FN7707.5
October 13, 2016
Submit Document Feedback
Ordering Information
PART NUMBER
(Notes 3, 4)
PART
MARKING
TEMP
RANGE (°C)
INPUT
CONFIGURATION
INPUT
LOGIC
PACKAGE
(RoHS COMPLIANT)
PKG.
DWG. #
ISL89163FRTAZ (Note 1
) 163A -40 to +125 Non-inverting 3.3V 8 Ld 3x3 TDFN L8.3x3I
ISL89163FRTBZ (Note 1) 163B -40 to +125 5.0V 8 Ld 3x3 TDFN L8.3x3I
ISL89164FRTAZ (Note 1) 164A -40 to +125 Inverting 3.3V 8 Ld 3x3 TDFN L8.3x3I
ISL89164FRTBZ (Note 1) 164B -40 to +125 5.0V 8 Ld 3x3 TDFN L8.3x3I
ISL89165FRTAZ (Note 1) 165A -40 to +125 Inverting +
Non-inverting
3.3V 8 Ld 3x3 TDFN L8.3x3I
ISL89165FRTBZ (Note 1) 165B -40 to +125 5.0V 8 Ld 3x3 TDFN L8.3x3I
ISL89163FBEAZ (Note 2) 89163 FBEAZ -40 to +125 Non-inverting 3.3V 8 Ld EPSOIC M8.15D
ISL89163FBEBZ (Note 2) 89163 FBEBZ -40 to +125 5.0V 8 Ld EPSOIC M8.15D
ISL89164FBEAZ (Note 2) 89164 FBEAZ -40 to +125 Inverting 3.3V 8 Ld EPSOIC M8.15D
ISL89164FBEBZ (Note 2) 89164 FBEBZ -40 to +125 5.0V 8 Ld EPSOIC M8.15D
ISL89165FBEAZ (Note 2) 89165 FBEAZ -40 to +125 Inverting +
Non-inverting
3.3V 8 Ld EPSOIC M8.15D
ISL89165FBEBZ (Note 2
) 89165 FBEBZ -40 to +125 5.0V 8 Ld EPSOIC M8.15D
NOTES:
1. Add “-T”, suffix for 6k unit tape and reel. Refer to TB347
for details on reel specifications.
2. Add “-T”, suffix for 2.5k unit tape and reel. Refer to TB347
for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. Input Logic Voltage: A = 3.3V, B = 5.0V.
5. For Moisture Sensitivity Level (MSL), see device information page for ISL89163
, ISL89164, ISL89165. For more information on MSL, see Technical
Brief TB363
.
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART NUMBER
I/O PINS
ENA ENB INA INB OUTA OUTB
ISL89163 NINV NINV NINV NINV NINV NINV
ISL89164 NINV NINV INV INV NINV NINV
ISL89165 NINV NINV INV NINV NINV NINV
NOTE: INV: Inverting Input, NINV: Non-inverting input.

ISL89165FRTAZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Gate Drivers 6A PEAK HI SPD PWR MSFT DRVR 8LD 3X3
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union