ISL89163, ISL89164, ISL89165
7
FN7707.5
October 13, 2016
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Test Waveforms and Circuits
FIGURE 4. PROP DELAYS AND MATCHING FIGURE 5. RISE/FALL TIMES
FIGURE 6. MILLER PLATEAU SINK CURRENT TEST CIRCUIT FIGURE 7. MILLER PLATEAU SOURCE CURRENT TEST CIRCUIT
FIGURE 8. MILLER PLATEAU SINK CURRENT FIGURE 9. MILLER PLATEAU SOURCE CURRENT
INA, INB,
ENA, ENB
OUTA
OUTB
0V
3.3V Option A
5.0V Option B
t
RDLY
t
RDLY
50% 50%
t
FDLY
t
FDLY
LOGIC LEVELS: OPTION A = 3.3V, OPTION B = 5.0V, OPTION C = V
DD
t
RM
t
FM
/OUTB
/OUTA
INA, INB,
ENA, ENB
0V
V
DD
80%
20%
Option C
Option A or B
OUTA
OR
OUTB
t
R
t
F
90%
10%
V
MILLER
10V
+I
SENSE
-I
SENSE
10µF
0.1µF
50m
200ns
10k
ISL8916x
10nF
V
MILLER
10V
+I
SENSE
-I
SENSE
10µF
0.1µF
50m
200ns
10k
ISL8916x
10nF
200ns
V
MILLER
-I
MP
V
OUT
CURRENT THROUGH 0.1
RESISTOR
10V
0A
0V
200ns
V
MILLER
I
MP
V
OUT
CURRENT THROUGH 0.1
RESISTOR
0
ISL89163, ISL89164, ISL89165
8
FN7707.5
October 13, 2016
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FIGURE 10. START-UP OUTPUT CHARACTERISTIC
Test Waveforms and Circuits
UV THRESHOLD
~1V
400µs TYPICAL
(T
on_delay
)
OUTA, OUTB
OUTPUT STATE
OUTPUTS CONTROLLED BY
LOGICAL INPUTS
10k to
GROUND
OUTPUTS
ACTIVE LOW
<1 to GROUND
RISING V
DD
THIS DURATION IS
DEPENDANT ON RISE TIME
OF VDD
THIS DURATION IS
INDEPENDENT ON
RISE TIME OF V
DD
Typical Performance Curves
FIGURE 11. I
DD
vs V
DD
(STATIC) FIGURE 12. I
DD
vs V
DD
(1MHz)
2.0
2.5
3.0
3.5
4 8 12 16
STATIC BIAS CURRENT (mA)
V
DD
+125°C
+25°C
-40°C
+125°C
+25°C
-40°C
20
25
30
35
15
10
5
4 8 12 16
1MHz BIAS CURRENT (mA)
V
DD
ISL89163, ISL89164, ISL89165
9
FN7707.5
October 13, 2016
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FIGURE 13. I
DD
vs FREQUENCY (+25°C) FIGURE 14. r
DS(ON)
vs TEMPERATURE
FIGURE 15. OPTION A THRESHOLDS FIGURE 16. OPTION B THRESHOLDS
FIGURE 17. OUTPUT RISE/FALL TIME FIGURE 18. PROPAGATION DELAY vs V
DD
Typical Performance Curves (Continued)
50
40
30
20
10
0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.6 2.0
FREQUENCY (MHz)
I
DD
(mA)
NO LOAD
5V
10V
16V
12V
1.81.4
0.5
0.6
0.7
0.8
0.9
1.0
1.1
-45 -20 5 30 55 80 105 130
r
DS(ON)
(Ω)
TEMPERATURE (°C)
V
OUT
LOW
V
OUT
HIGH
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-45 -20 5 30 55 80 105 130
INPUT LOGIC THRESHOLDS (3.3V)
TEMPERATURE (°C)
POSITIVE THRESHOLD
NEGATIVE THRESHOLD
3.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
-45 -20 5 30 55 80 105 130
INPUT LOGIC THRESHOLDS (3.3V)
TEMPERATURE (°C)
POSITIVE THRESHOLD
NEGATIVE THRESHOLD
3.5
15
20
25
-45 -20 5 30 55 80 105 130
RISE/FALL TIME (ns)
TEMPERATURE (°C)
FALL TIME, C
LOAD
= 10nF
RISE TIME, C
LOAD
= 10nF
15
20
25
30
5 7 9 11 13 15
PROPAGATION DELAY (ns)
V
DD
OUTPUT FALLING PROP DELAY
OUTPUT RISING PROP DELAY

ISL89165FRTAZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Gate Drivers 6A PEAK HI SPD PWR MSFT DRVR 8LD 3X3
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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