ISL89163, ISL89164, ISL89165
10
FN7707.5
October 13, 2016
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Functional Description
Overview
The ISL89163, ISL89164, ISL89165 MOSFET drivers incorporate
several features optimized for Synchronous Rectifier (SR) driver
applications including precision input logic thresholds, enable
inputs, undervoltage lockout, and high amplitude output drive
currents.
The precision input thresholds facilitate the use of an external RC
network to delay the rising or falling propagation of the driver
output. This is a useful feature for adjusting when the SRs turn on
relative to the primary side FETs. In a similar manner, these
drivers can also be used to control the turn-on/off timing of the
primary side FETs.
The Enable inputs (ENA, ENB) are used to emulate diode
operation of the SRs by disabling the driver output when it is
necessary to prevent negative currents in the output filter
inductors. An example is turning off the SRs when the power
supply output is turned off. This prevents the output capacitor
from being discharged through the output inductor. If this is
allowed to happen, the voltage across the output capacitor will
ring negative possibly damaging the capacitor (if it is polarized)
and probably damaging the load. Another example is preventing
circulating currents between paralleled power supplies during no
or light load conditions. During light load conditions (especially
when active load sharing is not active), energy will be transferred
from the paralleled power supply that has a higher voltage to the
paralleled power supply with the lower voltage. Consequently, the
energy that is absorbed by the low voltage output is then
transferred to the primary side causing the bus voltage to
increase until the primary side is damaged by excessive voltage.
The start-up sequence for input threshold Options A, B, and C is
designed to prevent unexpected glitches when V
DD
is being
turned on or turned off. When V
DD
< ~1V, an internal 10kΩ
resistor connected between the output and ground, help to keep
the gate voltage close to ground. When ~1V < V
DD
< UV, both
outputs are driven low while ignoring the logic inputs. This low
state has the same current sinking capacity as during normal
operation. This insures that the driven FETs are held off even if
there is a switching voltage on the drains that can inject charge
into the gates via the Miller capacitance. When V
DD
> UVLO, and
after a 400µs delay, the outputs now respond to the logic inputs.
See Figure 10
for complete details.
For the negative transition of V
DD
through the UV lockout voltage,
the outputs of input threshold Options A or B are active low when
V
DD
< ~3.2V
DC
regardless of the input logic states. Similarly, the
C option outputs are active low when V
DD
< ~6.5V
DC
.
Application Information
Precision Thresholds for Time Delays
Three input logic voltage levels are supported by the ISL89163,
ISL89164, ISL89165. Option A is used for 3.3V logic, Option B is
used for 5.0V logic, and Option C is used for higher voltage logic
when it is desired to have voltage thresholds that are
proportional to V
DD
. The A and B options have nominal
thresholds that are 37% and 63% of 3.3V and 5.0V respectively
and the C option is 20% and 80% of V
DD
.
In Figure 19
, R
del
and C
del
delay the rising edge of the input
signal. For the falling edge of the input signal, the diode shorts
out the resistor resulting in a minimal falling edge delay.
The 37% and 63% thresholds of Options A and B were chosen to
simplify the calculations for the desired time delays. When using
an RC circuit to generate a time delay, the delay is simply
T (secs) = R (ohms) x C (farads). Please note that this equation
only applies if the input logic voltage is matched to the 3.3V or 5V
threshold options. If the logic high amplitude is not equal to 3.3V
or 5V, then the equations shown in Equation 1
can be used for
more precise delay calculations.
In this example, the high logic voltage is 10V, the positive
threshold is 63% of 5V and the low level logic is 0.3V. Note the
rising edge propagation delay of the driver must be added to this
value.
The minimum recommended value of C is 100pF. The parasitic
capacitance of the PCB and any attached scope probes will
introduce significant delay errors if smaller values are used.
Larger values of C will further minimize errors.
Acceptable values of R are primarily effected by the source
resistance of the logic inputs. Generally, 100Ω resistors or larger
are usable.
Paralleling Outputs to Double the Peak Drive
Currents
The typical propagation matching of the ISL89163 and
ISL89164 is less than 1ns. The matching is so precise that
carefully matched and calibrated scopes probes and scope
channels must be used to make this measurement. Because of
this excellent performance, these driver outputs can be safely
paralleled to double the current drive capacity. It is important
that the INA and INB inputs be connected together on the PCB
with the shortest possible trace. This is also required of OUTA and
OUTB. Note that the ISL89165 cannot be paralleled because of
the complementary logic.
ENx
INx
R
del
c
del
D
OUTx
FIGURE 19. DELAY USING RCD NETWORK
V
H
10V
High level of the logic signal into the RC
V
thres
63% 5 V
Positive going threshold for 5V logic (B option)
V
L
.3V
Low level of the logic signal into the RC
R
del
100
Timing values
C
del
1nF
t
del
R
del
C
del
ln
V
L
V
thres
V
H
V
L
1
t
del
34.788 ns
nominal delay time for this example
