8430-61 Datasheet
©2016 Integrated Device Technology, Inc Revision D January 8, 20162
will automatically occur during power-up. The TEST output is
LOW when operating in the parallel input mode. The relationship
between the VCO frequency, the crystal frequency and the M
divider is defi ned as follows:
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Function
Table. Valid M values for which the PLL will achieve lock for a
16MHz reference are defi ned as 250 ≤ M ≤ 500. The frequency
out is defi ned as follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift
register are loaded into the M divider and N output divider when
S_LOAD transitions from LOW-to-HIGH. The M divide and N
output divide values are latched on the HIGH-to-LOW transition
of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is
passed directly to the M divider and N output divider on each ris-
ing edge of S_CLOCK. The serial mode can be used to program
the M and N bits and test bits T1 and T0. The internal registers
T0 and T1 determine the state of the TEST output as follows:
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes oper-
ation using a 16MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defi ned in the Input
Frequency Characteristics, Table 5, NOTE 1.
The 8430-61 features a fully integrated PLL and therefore re-
quires no external components for setting the loop bandwidth.
A parallel-resonant, fundamental crystal is used as the input to
the on-chip oscillator. The output of the oscillator is divided by 16
prior to the phase detector. With a 16MHz crystal, this provides
a 1MHz reference frequency. The VCO of the PLL operates over
a range of 250MHz to 500MHz. The output of the M divider is
also applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting
the VCO control voltage. Note that for some values of M (either
too high or too low), the PLL will not achieve lock. The output
of the VCO is scaled by a divider prior to being sent to each of
the LVPECL output buffers. The divider provides a 50% output
duty cycle.
The programmable features of the 8430-61 support two input
modes and to program the M divider and N output divider. The
two input operational modes are parallel and serial. Figure 1
shows the timing diagram for each mode. In parallel mode, the
nP_LOAD input is initially LOW. The data on inputs M0 through
M8 and N0 through N2 is passed directly to the M divider and N
output divider. On the LOW-to-HIGH transition of the nP_LOAD
input, the data is latched and the M divider remains loaded until
the next LOW transition on nP_LOAD or until a serial event
occurs. As a result, the M and N bits can be hard-wired to set
the M divider and N output divider to a specifi c default state that
T1 T0 TEST Output
0 0 LOW
0 1 S_Data, Shift Register Input
1 0 Output of M divider
1 1 CMOS Fout
16
M
fVCO =
fxtal
x
N
fout
=
fVCO
=
16
M
fxtal
x
N
