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8430AY-61LF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
8430-61 Datasheet
©2016 Integrated Device Technology, Inc Revision D January 8, 20164
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR nP_LOAD M N S_LOAD S_CLOCK S_DATA
H X X X X X X Reset. Forces outputs LOW.
L L Data Data X X X
Data on M and N inputs passed directly to the M divider
and N output divider. TEST output forced LOW.
L
↑
Data Data L X X
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
LH XXL
↑
Data
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
LH XX ↑ L Data
Contents of the shift register are passed to the
M divider and N output divider.
LH XX
↓
L Data M divider and N output divider values are latched.
L H X X L X X Parallel or serial input do not affect shift registers.
LH XXH
↑
Data S_DATA passed directly to M divider as it is clocked.
NOTE: L = LOW
H = HIGH
X = Don’t care
↑ = Rising edge transition
↓ = Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
VCO Frequency
(MHz)
M Divide
2561286432168421
M8 M7 M6 M5 M4 M3 M2 M1 M0
250 250 011111010
251 251 011111011
252 252 011111100
253 253 011111101
• • •••••••••
• • •••••••••
498 498 111110010
499 499 111110011
500 500 111110100
NOTE 1: These M divide values and the resulting frequencies correspond to a TEST_CLK or crystal frequency of 16MHz.
Inputs
N Divider Value
Output Frequency (MHz)
N2 N1 N0 Minimum Maximum
0 0 0 1 250 500
0 0 1 1.5 166.66 333.33
0 1 0 2 125 250
0 1 1 3 83.33 166.66
1 0 0 4 62.5 125
1 0 1 6 41.66 83.33
1 1 0 8 31.25 62.5
1 1 1 12 20.83 41.66
8430-61 Datasheet
©2016 Integrated Device Technology, Inc Revision D January 8, 20165
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V
CC
= V
CCA
= 3.3V±5%, V
CCO
= 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifi cations only. Functional
operation of product at these conditions or any conditions
beyond those listed in the DC Characteristics or AC Charac-
teristics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
CC
4.6V
Inputs, V
I
-0.5V to V
CC
+ 0.5V
Outputs, I
O
Continuous Current 50mA
Surge Current 100mA
Package Thermal Impedance, θ
JA
47.9°C/W (0 lfpm)
Storage Temperature, T
STG
-65°C to 150°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
CC
Core Supply Voltage 3.135 3.3 3.465 V
V
CCA
Analog Supply Voltage 3.135 3.3 V
CC
V
V
CCO
Output Supply Voltage
3.135 3.3 3.465 V
2.375 2.5 2.625 V
I
EE
Power Supply Current 155 mA
I
CCA
Analog Supply Current 15 mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, V
CC
= V
CCA
= 3.3V±5%, V
CCO
= 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input
High Voltage
M0:M8, N0:N2, MR, S_LOAD,
S_DATA, S_CLOCK, nP_
LOAD, VCO_SEL, XTAL_SEL
2V
CC
+ 0.3 V
TEST_CLK 2 V
CC
+ 0.3 V
V
IL
Input
Low Voltage
M0:M8, N0:N2, MR, S_LOAD,
S_DATA, S_CLOCK, nP_
LOAD, VCO_SEL, XTAL_SEL
-0.3 0.8 V
TEST_CLK -0.3 1.3 V
I
IH
Input
High Current
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK, S_
DATA, S_LOAD, nP_LOAD
V
CC
= V
IN
= 3.465V 150 µA
M5, XTAL_SEL, VCO_SEL V
CC
= V
IN
= 3.465V 5 µA
I
IL
Input
Low Current
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK, S_
DATA, S_LOAD, nP_LOAD
V
CC
= 3.465V,
V
IN
= 0V
-5 µA
M5, XTAL_SEL, VCO_SEL
V
CC
= 3.465V,
V
IN
= 0V
-150 µA
V
OH
Output High
Voltage
TEST; NOTE 1 V
CC
= 3.465V 2.6 V
V
OL
Output
Low Voltage
TEST; NOTE 1 0.5 V
NOTE 1: Outputs terminated with 50Ω to V
CC
/2.
8430-61 Datasheet
©2016 Integrated Device Technology, Inc Revision D January 8, 20166
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, V
CC
= V
CCA
= 3.3V±5%, V
CCO
= 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
IN
Input
Frequency
TEST_CLK; NOTE 1 14 27 MHz
XTAL_IN XTAL_OUT NOTE 1 14 27 MHz
S_CLOCK 50 MHz
NOTE 1: For the input crystal and TEST_CLK frequency range, the M value must be set for the VCO to operate within
the 250MHz to 500MHz range. Using the minimum input frequency of 14MHz, valid values of M are 286 ≤ M ≤ 511.
Using the maximum input frequency of 27MHz, valid values of M are 149 ≤ M ≤ 296.
TABLE 6. CRYSTAL CHARACTERISTICS
TABLE 4C. LVPECL DC CHARACTERISTICS, V
CC
= V
CCA
= 3.3V±5%, V
CCO
= 3.3V±5% OR 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
OH
Output High Voltage; NOTE 1 V
CCO
- 1.4 V
CCO
- 0.9 V
V
OL
Output Low Voltage; NOTE 1 V
CCO
- 2.0 V
CCO
- 1.7 V
V
SWING
Peak-to-Peak Output Voltage Swing 0.6 1.0 V
NOTE 1: Outputs terminated with 50Ω to V
CCO
- 2V. See “Parameter Measurement Information” section,
“Output Load Test Circuit” diagrams.
Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
Frequency 14 27 MHz
Equivalent Series Resistance (ESR) 50
Ω
Shunt Capacitance 7pF
Drive Level 1mW
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

8430AY-61LF

Mfr. #:
Buy 8430AY-61LF
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner Frequency Synthesizer
Lifecycle:
New from this manufacturer.
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