8430-61 Datasheet
©2016 Integrated Device Technology, Inc Revision D January 8, 20167
TABLE 7A. AC CHARACTERISTICS, V
CC
= V
CCA
= V
CCO
= 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
F
OUT
Output Frequency 20.83 500 MHz
tjit(cc) Cycle-to-Cycle Jitter; NOTE 1, 2
N ≠ 1.5
30 ps
N = 1.5 100 ps
tjit(per) Period Jitter, RMS; NOTE 1
N ≠ 1.5
6ps
tsk(o) Output Skew; NOTE 2, 3 15 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 200 700 ps
t
S
Setup Time
M, N to nP_LOAD 5 ns
S_DATA to S_CLOCK 5 ns
S_CLOCK to S_LOAD 5 ns
t
H
Hold Time
M, N to nP_LOAD 5 ns
S_DATA to S_CLOCK 5 ns
S_CLOCK to S_LOAD 5 ns
odc Output Duty Cycle
Even N divides 48 52 %
Odd N divides 45 55 %
t
LOCK
PLL Lock Time 1ms
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
TABLE 7B. AC CHARACTERISTICS, V
CC
= V
CCA
= 3.3V±5%, V
CCO
= 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
F
OUT
Output Frequency 20.83 500 MHz
tjit(cc) Cycle-to-Cycle Jitter; NOTE 1, 2
N ≠ 1.5
35 ps
N = 1.5 140 ps
tjit(per) Period Jitter, RMS; NOTE 1
N ≠ 1.5
6ps
tsk(o) Output Skew; NOTE 2, 3 30 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 200 700 ps
t
S
Setup Time
M, N to nP_LOAD 5 ns
S_DATA to S_CLOCK 5 ns
S_CLOCK to S_LOAD 5 ns
t
H
Hold Time
M, N to nP_LOAD 5 ns
S_DATA to S_CLOCK 5 ns
S_CLOCK to S_LOAD 5 ns
odc Output Duty Cycle
Even N divides 47 53 %
Odd N divides 45 55 %
t
LOCK
PLL Lock Time 1ms
See Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: This parameter is defi ned in accordance with JEDEC Standard 65.
NOTE 3: Defi ned as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
