8430-61 Datasheet
©2016 Integrated Device Technology, Inc Revision D January 8, 201610
INPUTS:
CRYSTAL INPUT:
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left fl oating. Though
not required, but for additional protection, a 1kΩ resistor can be
tied from XTAL_IN to ground.
TEST_CLK I
NPUT:
For applications not requiring the use of the test clock, it can be
left fl oating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the TEST_CLK to ground.
LVCMOS C
ONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
TEST OUTPUT:
The unused TEST output can be left fl oating. There should be
no trace attached.
LVPECL OUTPUT
All unused LVPECL outputs can be left fl oating. We recommend
that there is no trace attached. Both sides of the differential
output pair should either be left fl oating or terminated.
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 4. The XTAL_OUT pin can be left fl oating. The
input edge rate can be as slow as 10ns. For LVCMOS inputs,
it is recommended that the amplitude be reduced from full
swing to half swing in order to prevent signal interference with
the power rail and to reduce noise. This confi guration requires
FIGURE 4. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
that the output impedance of the driver (Ro) plus the series
resistance (Rs) equals the transmission line impedance. In
addition, matched termination at the crystal input will attenuate
the signal in half. This can be done in one of two ways. First, R1
and R2 in parallel should equal the transmission line impedance.
For most 50Ω applications, R1 and R2 can be 100Ω. This can
also be accomplished by removing R1 and making R2 50Ω.
R2
Zo = 50
VDD
Ro
Zo = Ro + Rs
R1
VDD
XTAL_IN
XTAL_OUT
.1uf
Rs
8430-61 Datasheet
©2016 Integrated Device Technology, Inc Revision D January 8, 201611
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
50Ω transmission lines. Matched impedance techniques should
FIGURE 5B. LVPECL OUTPUT TERMINATION
FIGURE 5A. LVPECL OUTPUT TERMINATION
be used to maximize operating frequency and minimize signal
distortion. There are a few simple termination schemes. Figures
5A and 5B show two different layouts which are recommended
only as guidelines. Other suitable clock layouts may exist and
it would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
TERMINATION FOR 3.3V LVPECL OUTPUTS
8430-61 Datasheet
©2016 Integrated Device Technology, Inc Revision D January 8, 201612
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 6A and Figure 6B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to V
CC
- 2V. For V
CCO
= 2.5V, the V
CCO
- 2V is very close to
ground level. The R3 in Figure 6B can be eliminated and the
termination is shown in Figure 6C.
FIGURE 6C. 2.5V LVPECL TERMINATION EXAMPLE
R2
50
Zo = 50 Ohm
VCCO=2.5V
R1
50
Zo = 50 Ohm
+
-
2.5V
2,5V LVPECL
Driver
FIGURE 6B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
VCCO=2.5V
R1
50
R2
50
Zo = 50 Ohm
R3
18
2,5V LVPECL
Driver
Zo = 50 Ohm
+
-
2.5V
FIGURE 6A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
R2
62.5
2.5V
2,5V LVPECL
Driver
R3
250
Zo = 50 Ohm
Zo = 50 Ohm
R4
62.5
2.5V
+
-
R1
250
VCCO=2.5V

8430AY-61LF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner Frequency Synthesizer
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