Si85xx
Preliminary Rev. 0.4 11
Integrator reset Option 1 is selected by connecting T
RST
to VDD. In this mode, the Si85xx is held in reset as long
as the signals on R1–R4 satisfy the logic equations of
Table 11. It is typically used in applications where the
gate drivers are external to the system controller IC (the
gate driver delay ensures reset is completed prior to the
start of measurement).
Reset Option 2 is selected by connecting a timing
resistor (R
TRST
in Figure 5) from the TRST input to
ground. It is typically used in applications where the
gate drivers are on-board the controller. In this mode,
the on-chip reset timer is triggered when the signals on
R1–R4 satisfy the logic equations in Table 11. Once
triggered, the timer maintains integrator in reset for time
duration t
R
as programmed by the value of resistor
R
TRST
. The user must select the value of resistor R
TRST
to terminate the reset cycle prior to the start of
measurement under worst-case timing conditions. Note
that values of t
R
below the specified value in "1.
Electrical Specifications" on page 4 results in increased
integrator output offset error and increased output noise
on V
OUT
. Moreover, t
R
’s time is summarized by the
following equation (see Table 9):
t
R
= 10 ns/k
where values of R
TRST
that produce a reset time less
than 150 ns (R
TRST
< 15 k) should not be used.
Figure 5. Programming Reset Time (t
R
)
2.4. Total Measurement Error
The Si85xx’s absolute accuracy is affected by the
following factors:
Ambient operating temperature
VDD supply voltage
Time
Table 10 includes a composite of all environmental and
operating conditions that can ultimately affect the
absolute measurement accuracy of the Si85xx. The
total worst-case accuracy at full scale can be estimated
by the sum of the initial accuracy (up to ±5%) plus aging
(up to ±1.5%) and supply variations (up to ±3.5%). For
example, the total measurement error expected for a
device operating at a given V
DD
supply of 5 V (±10%) is
10% if the device is operated over a temperature range
of –40 to 125 °C for up to 10 years. If the temperature
range is limited to 0 to 85 °C, the measurement error
can be improved by up to 2%. See Figure 6 for details.
2.5. Effect of Temperature on Accuracy
Offset voltage present at the Si85xx output terminals
(output offset voltage) is calibrated out each time VDD is
applied to the Si85xx; so, its error contribution is
minimized when the temperature at which calibration
occurred is at or near the steady-state operating
temperature of the Si85xx. For example, applying VDD
at 25 °C (offset cal is performed) and operating at 85 °C
will result in a larger offset error than operating at 50 °C.
The effect of this error is summarized in Figure 6. The
chart is referenced to 25 °C. If the Si85xx is powered up
at 25 °C and then operated at 125 °C with no auto-
calibration performed (i.e., the power is not cycled at
125 °C, which causes an auto-calibration), a 3%
measurement error can be expected.
Table 9. Typical Reset Time vs. R
TRST
Resistance
R
TRST
Reset Time (t
R
)
15 k 150 ns
100 k 1µs
1M 9µs
2.2 M 20 µs
Table 10. Total Measurement Error Contributors
Error Contributor % Error Added
Initial error
@ given V
DD
±10%, 25 °C
±5%
Temperature variation
–40 to 125 °C
±3.5%
Aging (10 years) ±1.5%
