Si85xx
Preliminary Rev. 0.4 17
As explained in Section “2.3. Integrator Reset and Current Measurement”, the signals applied to R1–R4 can
control integrator reset in real time (Option 1), or they can trigger a reset event of programmable duration (Option
2). Referring to Figure 14, reset timing is exclusively a function of the signals applied to R1–R4 when TRST is tied
to VDD.
If not connected to VDD, the reset timer is enabled, and TRST must be connected through a resistor to ground to
set the reset duration (t
R
). Note that the reset timer is retriggerable and generates a timed integrator discharge
pulse whenever the reset logic output transitions from low to high.
Figure 14. Si851x Integrator Reset Logic
R4
R2
R1
R3
INTEGRATOR
MODE = 1
R4 = 0
MODE = 1
R4 = 1
MODE = 0
SYSTEM
CONTROLLER
Logic level gate
control signals
(to Rn inputs)
Logic level gate
control signals
(to Rn inputs)
External
Driver
Internal
Driver
Required if driver
output voltage > VDD
Output 1
Output 2
Output 3
RESET
TIMER
OUT
CLK
TRST
PGM
VREF
Reset timing determined
only by inputs R1–R4.
Reset triggered by inputs
R1–R4. Reset time (t
R
) set
by value of resistor R
TRST
.
TRST = R1 to GND
TRST = VDD
0
+
1
