AD977/AD977A
–13–REV. D
EXTERNAL CONTINUOUS CLOCK DATA READ DURING
CONVERSION WITH SYNC OUTPUT GENERATED
Figure 9 illustrates the method by which data from conversion
“n-1” can be read during conversion “n” while using a continu-
ous external clock with the generation of a SYNC output. What
permits the generation of a SYNC output is a transition of
DATACLK while either CS is high or while both CS and R/C
are low.
With a continuous clock the CS pin cannot be tied low as it
could be with a discontinuous clock. Use of a continuous clock
while a conversion is occurring can increase the DNL and
Transition Noise of the AD977/AD977A.
In Figure 9 a conversion is initiated by taking R/C low with CS
held low. While this condition exists a transition of DATACLK,
clock pulse #0, will enable the generation of a SYNC pulse.
Less then 83 ns after R/C is taken low the BUSY output will go
low to indicate that the conversion process has began. Figure 9
shows R/C then going high and after a delay of greater than
15 ns (t
15
), clock pulse #1 can be taken high to request the
SYNC output. The SYNC output will appear approximately
50 ns after this rising edge and will be valid on the falling edge
of clock pulse #1 and the rising edge of clock pulse #2. The
MSB will be valid approximately 40 ns after the rising edge of
clock pulse #2 and can be latched off either the falling edge of
clock pulse #2 or the rising edge of clock pulse #3. The LSB
will be valid on the falling edge of clock pulse #17 and the rising
edge of clock pulse #18. Approximately 40 ns after the rising
edge of clock pulse #18, the DATA output pin will reflect the
state of the TAG input pin during the rising edge of clock
pulse #2.
For both the AD977 and the AD977A the data should be
clocked out during the 1st half of BUSY so as not to degrade
conversion performance. For the AD977 this requires use of a
4.8 MHz DATACLK or greater with data being read out as
soon as the conversion process begins. For the AD977A it
requires use of a 10 MHz DATACLK or greater.
CS
BUSY
R/C
EXT
DATACLK
BIT 15
(MSB)
1
DATA
SYNC
03
BIT 0
(LSB)
TAG 0 TAG 1
TAG 0
TAG
2
t
13
t
14
t
12
t
19
18
t
15
t
16
t
1
t
20
t
2
t
17
t
12
t
18
t
23
t
24
t
18
TAG 2
TAG 1 TAG 16 TAG 17 TAG 18 TAG 19
Figure 9. Conversion and Read Timing for Reading Previous Conversion Results During a Conversion Using An External
Continuous Data Clock (EXT/
INT
Set to Logic High)
AD977/AD977A
–14–
REV. D
Table I. AD977A Analog Input Configuration
Input Voltage Connect R1
IN
Connect R2
IN
Connect R3
IN
Input
Range via 200 to via 100 to to Impedance
± 10 V V
IN
AGND 2.5 V 11.5 k
± 5 V AGND V
IN
2.5 V 6.7 k
± 3.3 V V
IN
V
IN
2.5 V 5.4 k
0 V to 10 V AGND V
IN
AGND 6.7 k
0 V to 5 V AGND AGND V
IN
5.0 k
0 V to 4 V V
IN
AGND V
IN
5.4 k
Table II. AD977 Analog Input Configuration
Input Voltage Connect R1
IN
Connect R2
IN
Connect R3
IN
Input
Range via 200 to via 100 to to Impedance
± 10 V V
IN
AGND CAP 22.9 k
± 5 V AGND V
IN
CAP 13.3 k
± 3.3 V V
IN
V
IN
CAP 10.7 k
0 V to 10 V AGND V
IN
AGND 13.3 k
0 V to 5 V AGND AGND V
IN
10.0 k
0 V to 4 V V
IN
AGND V
IN
10.7 k
ANALOG INPUTS
The AD977/AD977A is specified to operate with six full-scale
analog input ranges. Connections required for each of the three
analog inputs, R1
IN
, R2
IN
and R3
IN
, and the resulting full-scale
ranges, are shown in Table I and Table II. The nominal input
impedance for each analog input range is also shown. Table III
shows the output codes for the ideal input voltages of each of the
six analog input ranges.
The analog input section has a ± 25 V overvoltage protection on
R1
IN
and R2
IN
. Since the AD977/AD977A has two analog
grounds it is important to ensure that the analog input is refer-
enced to the AGND1 pin, the low current ground. This will
minimize any problems associated with a resistive ground drop.
It is also important to ensure that the analog input of the
AD977/AD977A is driven by a low impedance source. With its
primarily resistive analog input circuitry, the ADC can be driven
by a wide selection of general purpose amplifiers.
To best match the low distortion requirements of the AD977/
AD977A, care should be taken in the selection of the drive cir-
cuitry op amp.
Figure 10 shows the simplified analog input section for the
AD977/AD977A. Since the AD977/AD977A can operate with
an internal or external reference, and several different analog
input ranges, the full-scale analog input range is best represented
with a voltage that spans 0 V to V
REF
across the 40 pF sampling
capacitor. The onboard resistors are laser trimmed to ratio
match for adjustment of offset and full-scale error using fixed
external resistors.
The configurations shown in Figures 12 and 13 are required to
obtain the data sheet specifications for offset and full-scale error.
The external fixed resistors are used during factory calibration so
that a single 5 V supply can be used to bias the hardware trim
circuitry. With the hardware adjust circuits shown in Figures 12
and 13, offset and full-scale error can be trimmed to zero. Refer
to the Offset and Gain Adjust section.
If larger offset and full-scale errors are permitted, or if soft-
ware calibration is used, the external resistors can be omit-
ted. Table IV shows the resultant input ranges and offset and
full-scale errors.
Using the AD977A with Bipolar Input Ranges
The connection diagrams in Figure 11 show a buffer amplifier
required for bipolar operation of the AD977A when using the
internal reference. The buffer amplifier is required to isolate the
CAP pin from the signal dependent current in the R3
IN
pin. A
high speed op amp such as the AD8031 can be used with a
single 5 V power supply without degrading the performance of
the AD977A. The buffer must have good settling characteristics
and provide low total noise within the input bandwidth of the
AD977A.
R1
IN
R2
IN
R3
IN
REF
4k
AGND2
CAP
AGND1
AD977/AD977A
20k /10k
2.5V
REFERENCE
10k /5k
5k /2.5k
20k /10k
40pF
SWITCHED
CAP ADC
Figure 10. AD977/AD977A Simplified Analog Input
AD977/AD977A
–15–REV. D
Table III. Output Codes and Ideal Input Voltages
Digital Output
Two’s Complement Straight Binary
Description Analog Input (SB/BTC LOW) (SB/BTC HIGH)
Full-Scale Range ±10 V ± 5 V ±3.33 V 0 V to 10 V 0 V to 5 V 0 V to 4 V
Least Significant Bit 305 µV 153 µV 102 µV 153 µV 76 µV 61 µV
+Full Scale (FS–1 LSB) 9.999695 V 4.999847 V 3.333231 V 9.999847 V 4.999924 V 3.999939 V 0111 1111 1111 1111 1111 1111 1111 1111
Midscale 0 V 0 V 0 V 5 V 2.5 V 2 V 0000 0000 0000 0000 1000 0000 0000 0000
One LSB Below Midscale –305 µV –153 µV –102 µV 4.999847 V 2.499924 V 1.999939 V 1111 1111 1111 1111 0111 1111 1111 1111
–Full Scale –10 V –5 V –3.333333 V 0 V 0 V 0 V 1000 0000 0000 0000 0000 0000 0000 0000
Table IV. Input Ranges, Offset and Full-Scale Errors Without External Resistors
AD977 Offset Error Full-Scale Error AD977A Offset Error Full-Scale Error
Input Range A/B/C Grade A/B/C Grade Input Range A/B/C Grade A/B/C Grade
–9.890 V to 9.90 V ±25 mV/±25 mV ± 0.75%/± 0.50% –9.800 V to 9.970 V ±40 mV/±40 mV ± 0.80%/± 0.55%
–4.943 V to 4.995 V ±25 mV/±25 mV ± 0.75%/± 0.50% –4.900 V to 4.985 V ±40 mV/±40 mV ± 0.80%/± 0.55%
–3.295 V to 3.330 V ±25 mV/±25 mV ± 0.75%/± 0.50% –3.267 V to 3.323 V ±40 mV/±40 mV ± 0.80%/± 0.55%
0.008 V to 9.946 V ±10 mV/± 10 mV ± 0.75%/± 0.50% 0.007 V to 9.893 V ± 10 mV/±10 mV ± 0.75%/± 0.50%
0.004 V to 5.023 V ±10 mV/± 10 mV ± 0.75%/± 0.50% 0.004 V to 5.039 V ± 10 mV/±10 mV ± 0.75%/± 0.50%
0.003 V to 4.010 V ±10 mV/± 10 mV ± 0.75%/± 0.50% 0.003 V to 4.016 V ± 10 mV/±10 mV ± 0.75%/± 0.50%
200
V
IN
100
33.2k
2.2 F
2.2
F
R1
IN
R2
IN
R3
IN
REF
AGND2
CAP
AGND1
AD977A
AD8031
200
33.2k
2.2 F
2.2
F
R1
IN
R2
IN
R3
IN
REF
AGND2
CAP
AGND1
AD977A
V
IN
100
AD8031
200
V
IN
100
33.2k
2.2 F
2.2
F
R1
IN
R2
IN
R3
IN
REF
AGND2
CAP
AGND1
AD977A
AD8031
Figure 11. AD977A Bipolar Input Configuration Using the Internal Reference; (a) V
IN
=
±
10 V, (b) V
IN
=
±
5 V, (c) V
IN
=
±
3.33 V
a.
c.
b.

AD977ABRSZRL

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC 16-Bit 200 kSPS Serial I/O
Lifecycle:
New from this manufacturer.
Delivery:
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