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854S057AGILFT

P1-P3P4-P6P7-P9P10-P12P13-P15
DATA SHEET
4:1 or 2:1 LVDS Clock Multiplexer with
Internal Input Termination
854S057
854S057 Rev A 10/23/14 1 ©2014 Integrated Device Technology, Inc.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
nPCLK1
VT1
PCLK1
SEL0
SEL1
nPCLK0
VT0
PCLK0
V
DD
GND
V
DD
PCLK3
VT3
nPCLK3
Q
nQ
PCLK2
VT2
nPCLK2
GND
General Description
The 854S057 is a 4:1 or 2:1 LVDS Clock Multiplexer which can
operate up to 2GHz. The PCLK, nPCLK pairs can accept most
standard differential input levels. Internal termination is provided on
each differential input pair. The 854S057 operates using a 2.5V
supply voltage. The fully differential architecture and low propagation
delay make it ideal for use in high speed multiplexing applications.
The select pins have internal pulldown resistors. Leaving one input
unconnected (pulled to logic low by the internal resistor) will
transform the device into a 2:1 multiplexer. The SEL1 pin is the most
significant bit and the binary number applied to the select pins will
select the same numbered data input (i.e., 00 selects PCLK0,
nPCLK0).
Features
• High speed differential multiplexer. The device can be configured
as either a 4:1 or 2:1 multiplexer
• One LVDS output pair
• Four selectable PCLK, nPCLK inputs with internal termination
• PCLKx, nPCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, CML, SSTL
• Maximum output frequency: 2GHz
• Part-to-part skew: 200ps (maximum)
• Propagation delay: 650ps (maximum)
• Additive phase jitter, RMS: 0.047ps (typical)
• Full 2.5V power supply
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
0 0
0 1
1 0
1 1
Q
nQ
VT0
PCLK0
nPCLK0
SEL1
SEL0
50 50
VT1
PCLK1
nPCLK1
50 50
VT2
PCLK2
nPCLK2
50 50
VT3
PCLK3
nPCLK3
50 50
Pulldown
Pulldown
Pin Assignment
854S057
20-Lead TSSOP
4.4mm x 6.5mm x 0.925mm package body
G Package
Top View
Block Diagram
Rev A 10/23/14 2 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT
TERMINATION
854S057 DATA SHEET
Table 1. Pin Descriptions
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Table 3. Control Input Function Table
Number Name Type Description
1, 20 V
DD
Power Power supply pins.
2 PCLK0 Input Non-inverting LVPECL differential clock input. R
T
= 50 termination to VT0.
3 VT0 Input Termination input. For LVDS input, leave floating. R
T
= 50 termination to VT0.
4 nPCLK0 Input Inverting LVPECL differential clock input. R
T
= 50 termination to VT0.
5, 6 SEL1, SEL0 Input Pulldown Clock select inputs. LVCMOS/LVTTL interface levels.
7 PCLK1 Input Non-inverting LVPECL differential clock input. R
T
= 50 termination to VT1.
8 VT1 Input Termination input. For LVDS input, leave floating. R
T
= 50 termination to VT1.
9 nPCLK1 Input Inverting LVPECL differential clock input. R
T
= 50 termination to VT1.
10, 11 GND Power Power supply ground.
12 nPCLK2 Input Inverting LVPECL differential clock input. R
T
= 50 termination to VT2.
13 VT2 Input Termination input. For LVDS input, leave floating. R
T
= 50 termination to VT2.
14 PCLK2 Input Non-inverting LVPECL differential clock input. R
T
= 50 termination to VT2.
15, 16 nQ, Q Output Differential output pair. LVDS interface levels.
17 nPCLK3 Input Inverting LVPECL differential clock input. R
T
= 50 termination to VT3.
18 VT3 Input Termination input. For LVDS input, leave floating. R
T
= 50 termination to VT3.
19 PCLK3 Input Non-inverting LVPECL differential clock input. R
T
= 50 termination to VT3.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 2pF
R
PULLDOWN
Input Pulldown Resistor 50 k
R
T
Input Termination Resistor 40 50 60
Inputs Outputs
SEL1 SEL0 PCLKx, nPCLKx
0 (default) 0 (default) PCLK0, nPCLK0
0 1 PCLK1, nPCLK1
1 0 PCLK2, nPCLK2
1 1 PCLK3, nPCLK3
854S057 DATA SHEET
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT
TERMINATION
3 Rev A 10/23/14
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
DC Electrical Characteristics
Table 4A. LVDS Power Supply DC Characteristics, V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Table 4B. LVCMOS/LVTTL DC Characteristics, V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
Table 4C. LVPECL Differential DC Characteristics, V
DD
= 2.5V ± 5%, T
A
= -40°C to 85°C
NOTE 1: Guaranteed by design.
NOTE 2: Common mode input voltage is defined as V
IH
.
Item Rating
Supply Voltage, V
DD
4.6V
Inputs, V
I
-0.5V to V
DD
+ 0.5V
Outputs, I
O
Continuos Current
Surge Current
10mA
15mA
Input Current, PCLK, nPCLK ±50mA
V
T
Current, I
VT
±100mA
Package Thermal Impedance,
JA
92.1°C/W (0 mps)
Storage Temperature, T
STG
-65C to 150C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
DD
Power Supply Voltage 2.375 2.5 2.625 V
I
DD
Power Supply Current 50 mA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage V
DD
= 2.5V 1.7 V
DD
+ 0.3 V
V
IL
Input Low Voltage V
DD
= 2.5V -0.3 0.7 V
I
IH
Input High Current SEL0, SEL1 V
DD
= V
IN
= 2.625V 150 µA
I
IL
Input Low Current SEL0, SEL1 V
DD
= 2.625V, V
IN
= 0V -10 µA
Symbol Parameter Test Conditions Minimum Typical Maximum Units
I
IN
Absolute Input Current; NOTE 1 V
DD
= V
IN
= 2.625V 35 mA
V
PP
Peak-to-Peak Voltage 0.15 1.2 V
V
CMR
Common Mode Input Voltage; NOTE 2 GND + 1.2 V
DD
V
P1-P3P4-P6P7-P9P10-P12P13-P15

854S057AGILFT

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Clock Generators & Support Products 4:1 or 2:1 LVDS Clk Multiplexer w/int
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