854S057 DATA SHEET
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT
TERMINATION
9 Rev A 10/23/14
2.5V LVPECL Input with Built-In 50 Termination Interface
The PCLK /nPCLK with built-in 50 terminations accept LVDS,
LVPECL, CML, SSTL and other differential signals. Both differential
signals must meet the V
PP
and V
CMR
input requirements. Figures 2A
to 2E show interface examples for the PCLK /nPCLK with built-in 50
termination input driven by the most common driver types. The input
interfaces suggested here are examples only. If the driver is from
another vendor, use their termination recommendation. Please
consult with the vendor of the driver component to confirm the driver
termination requirements.
Figure 2A. PCLK/nPCLK Input with
Built-In 50 Driven by an LVDS Driver
Figure 2C. PCLK/nPCLK Input with
Built-In 50 Driven by a CML Driver
Figure 2E. PCLK/nPCLK Input with
Built-In 50 Driven by an SSTL Driver
Figure 2B. PCLK/nPCLK Input with
Built-In 50 Driven by an LVPECL Driver
Figure 2D. PCLK/nPCLK Input with Built-In 50 Driven
by a CML Driver with Built-In 50 Pullup
PCLK
nPCLK
VT
Receiver
With
Built-In
50
Ω
LVDS
3.3V or 2.5V
2.5V
Zo = 50
Ω
Zo = 50
Ω
PCLK
nPCLK
VT
CML
Receiver
With
Built-In
50Ω
2.5V2.5V
Zo = 50Ω
Zo = 50Ω
SSTL
R1 25Ω
R2 25Ω
PCLK
nPCLK
VT
Receiver
With
Built-In
50Ω
2.5V
2.5V
Zo = 50Ω
Zo = 50Ω
PCLK
nPCLK
VT
Receiver
With
Built-In
50Ω
R1
18
Ω
LVPECL
2.5V2.5V
Zo = 50Ω
Zo = 50Ω
CML - Built-in 50Ω Pull-up
PCLK
nPCLK
VT
Receiver
With
Built-In
50Ω
2.5V
2.5V
Zo = 50Ω
Zo = 50Ω
