Rev A 10/23/14 10 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT
TERMINATION
854S057 DATA SHEET
LVDS Driver Termination
A general LVDS interface is shown in Figure 3. Standard termination
for LVDS type output structure requires both a 100 parallel resistor
at the receiver and a 100 differential transmission line environment.
In order to avoid any transmission line reflection issues, the 100
resistor must be placed as close to the receiver as possible. IDT
offers a full line of LVDS compliant devices with two types of output
structures: current source and voltage source. The standard
termination schematic as shown in Figure 3 can be used with either
type of output structure. If using a non-standard termination, it is
recommended to contact IDT and confirm if the output is a current
source or a voltage source type structure. In addition, since these
outputs are LVDS compatible, the input receivers amplitude and
common mode input range should be verified for compatibility with
the output.
Figure 3. Typical LVDS Driver Termination
Schematic Example
Figure 4 shows a schematic example of the 854S057. In this
example, the PCLK0/nPCLK0 and PCLK1/nPCLK1 inputs are used.
The decoupling capacitors should be physically located near the
power pin.
Figure 4. 854S057 LVDS Schematic Example
100Ω
+
100
Ω
Differential Transmission Line
LVDS Driver
LVDS
Receiver
(U1,20)
R2
680
Zo = 50
Zo = 50
VDD
VDD
VDD
R3
680
Zo = 50
Zo = 50
R5
100
R1
680
U1 ICS854057
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
20
19
18
17
VDD
PCLK0
VT0
nPCLK0
SEL1
SEL0
PCLK1
VT1
nPCLK1
GND GND
nPCLK2
VT2
PCLK2
nQ
Q
VDD
PCLK3
VT3
nPCLK3
Zo = 50
VDD
VDD
LVDS
+
-
R4
680
R6
18
Zo = 50
VDD
VDD
VDD=2.5V
LVDS
R1
1K
LVPECL
C2
0.1u
(U1,1)
R1
1K
C1
0.1u
854S057 DATA SHEET
4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT
TERMINATION
11 Rev A 10/23/14
Power Considerations
This section provides information on power dissipation and junction temperature for the 854S057.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 854S057 is the sum of the core power plus the power dissipation in the load(s).
The following is the power dissipation for V
DD
= 2.5V + 5% = 2.625V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipation in the load.
Power (core)
MAX
= V
DD_MAX
* I
DD_MAX
= 2.625V * 50mA = 131.25mW
Power Dissipation for internal termination R
T
Power (R
T
)
MAX
= 4 * (V
PP_MAX
)
2
/ R
T_MIN
= (1.2V)
2
/ 80 = 72mW
Total Power_
MAX
= 131.25mW + 72mW = 203.25mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad, and directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj =
JA
* Pd_total + T
A
Tj = Junction Temperature
JA
= Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T
A
= Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance
JA
must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 92.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.203W * 92.1°C/W = 103.7°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 6. Thermal Resistance
JA
for 20 Lead TSSOP, Forced Convection
JA
by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 92.1°C/W 86.5°C/W 83.0°C/W
Rev A 10/23/14 12 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT
TERMINATION
854S057 DATA SHEET
Reliability Information
Table 7.
JA
vs. Air Flow Table for a 20 Lead TSSOP
Transistor Count
The transistor count for 854S057 is: 375
This device is pin and function compatible and a suggested replacement for ICS854057.
Package Outline and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP Table 8. Package Dimensions
Reference Document: JEDEC Publication 95, MO-153
JA
by Velocity
Meters per Second 012.5
Multi-Layer PCB, JEDEC Standard Test Boards 92.1°C/W 86.5°C/W 83.0°C/W
All Dimensions in Millimeters
Symbol Minimum Maximum
N 20
A 1.20
A1 0.05 0.15
A2 0.80 1.05
b 0.19 0.30
c 0.09 0.20
D 6.40 6.60
E 6.40 Basic
E1 4.30 4.50
e 0.65 Basic
L 0.45 0.75
aaa 0.10

854S057AGILFT

Mfr. #:
Manufacturer:
Description:
Clock Generators & Support Products 4:1 or 2:1 LVDS Clk Multiplexer w/int
Lifecycle:
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