854S057AGILFT Datasheet 854S057AGILF, 854S057AGILFT | P4-P6

Rev A 10/23/14 4 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT

TERMINATION

854S057 DATA SHEET

Table 4D. LVDS DC Characteristics, V

= 2.5V ± 5%, T

= -40°C to 85°C

Table 5. AC Characteristics, V

= 2.5V ± 5%, T

= -40°C to 85°C

NOTE: All parameters measured at ƒ  2GHz unless noted otherwise.

NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is

mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium

has been reached under these conditions.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between different devices operating at the same supply voltage, same frequency and with equal load conditions.

Using the same type of inputs on each device, the output is measured at the differential cross point.

NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.

Symbol Parameter Test Conditions Minimum Typical Maximum Units

Differential Output Voltage 247 325 454 mV

V

Magnitude Change 50 mV

Offset Voltage 1.125 1.25 1.375 V

V

Magnitude Change 5 50 mV

Symbol Parameter Test Conditions Minimum Typical Maximum Units

MAX

Output Frequency 2GHz

Propagation Delay; NOTE 1 150 650 ps

tsk(pp) Part-to-Part Skew; NOTE 2, 3 200 ps

tsk(i) Input Skew 60 ps

tjit

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

622.08MHz, Integration Range:

12kHz – 20MHz

0.047 ps

/ t

Output Rise/Fall Time 20% to 80% 50 250 ps

odc Output Duty Cycle

ƒ 700MHz 48 52 %

ƒ  1.1GHz 46 54 %

ƒ  2GHz 42 58 %

MUX

ISOLATION

MUX Isolation ƒ = 500MHz -65 dBm

854S057 DATA SHEET

4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT

TERMINATION

5 Rev A 10/23/14

Additive Phase Jitter

The spectral purity in a band at a specific offset from the fundamental

compared to the power of the fundamental is called the dBc Phase

Noise. This value is normally expressed using a Phase noise plot

and is most often the specified plot in many applications. Phase noise

is defined as the ratio of the noise power present in a 1Hz band at a

specified offset from the fundamental frequency to the power value of

the fundamental. This ratio is expressed in decibels (dBm) or a ratio

of the power in the 1Hz band to the power in the fundamental. When

the required offset is specified, the phase noise is called a dBc value,

which simply means dBm at a specified offset from the fundamental.

By investigating jitter in the frequency domain, we get a better

understanding of its effects on the desired application over the entire

time record of the signal. It is mathematically possible to calculate an

expected bit error rate given a phase noise plot.

As with most timing specifications, phase noise measurements has

issues relating to the limitations of the equipment. Often the noise

floor of the equipment is higher than the noise floor of the device. This

is illustrated above. The device meets the noise floor of what is

shown, but can actually be lower. The phase noise is dependent on

the input source and measurement equipment.

The source generator "Rohde & Schwarz SMA100A Low Noise

Signal Generator as external input to an Agilent 8133A 3GHz Pulse

Generator".

SSB Phase Noise dBc/Hz

Offset from Carrier Frequency (Hz)

Additive Phase Jitter @ 622.08MHz

12kHz to 20MHz = 0.047ps (typical)

Rev A 10/23/14 6 4:1 OR 2:1 LVDS CLOCK MULTIPLEXER WITH INTERNAL INPUT

TERMINATION

854S057 DATA SHEET

Parameter Measurement Information

LVDS Output Load AC Test Circuit

MUX Isolation

Input Skew

Differential Input Level

Part-to-Part Skew

Propagation Delay

SCOPE

2.5V±5%

POWER SUPPLY

+–

Float GND

Amplitude (dB)

Spectrum of Output Signal Q

MUX

_ISOL

= A0 – A1

(fundamental)

Frequency

MUX selects static input

MUX selects active

input clock signal

PD2

PD1

tsk(i) = |t

PD1

- t

PD2

tsk(i)

nPCLKx

PCLKx

nPCLKy

PCLKy

nPCLK[0:3]

PCLK[0:3]

GND

CMR

Cross Points

tsk(pp)

Part 1

Part 2

PCLK[0:3]

nPCLK[0:3]

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15

854S057AGILFT

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854S057AGILFT

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