Function description TDA7705
14/42 Doc ID 15938 Rev 9
The sequence consists of the following phases:
● START: SDA line transitioning from H to L with SCL fixed H. This signifies a new
transmission is starting;
● data latching: on the rising SCL edge. The SDA line can transition only when SCL is
low (otherwise its transitions are interpreted as either a START or a STOP transition);
● ACKnowledge: on the 9
th
SCL pulse the µP keeps the SDA line H, and the TDA7705
pulls it down if communication has been successful. Lack of the acknowledge pulse
generation from the TDA7705 means that the communication has failed;
● a chip address byte must be sent at the beginning of the transmission. The value can
be C2 or C8 (according to the mode chosen at start-up during boot) for "write";
● as many data bytes as needed can follow the address before the communication is
terminated. See the next section for details on the frame format;
● STOP: SDA line transitioning from L to H with SCL H. This signifies the end of the
transmission.
Red lines represent transmissions from the TDA7705 to the µP.
A "read" communication example is shown in the figure below, for an unspecified number of
data bytes (see later on for frame structure decription):
Figure 4. I
2
C "read" sequence
The sequence is very similar to the "write" one and has the same constraints for start, stop,
data latching. The differences follow:
● a chip address must always be sent by the µP to the TDA7705; the address must be C3
(if C2 had been selected at boot) or C9 (if C8 had been selected at boot);
● a header is transmitted after the chip address (the same happens for "write") before
data are transferred from the TDA7705 to the µP. See the relevant technical
documentation for details on the frame format;
● when data are transmitted from the TDA7705 to the µP, the µP keeps the SDA line H;
● the ACKnowledge pulse is generated by the µP for those data bytes that are sent by the
TDA7705 to the µP. Failure of the µP to generate an ACK pulse on the 9
th
CLK pulse
has the same effect on the TDA7705 as a STOP.
The max. clock speed is 500 kbit/s.
2.13.3 SPI bus protocol
SPI requires four signals: clock (CLK), master output/slave input (MOSI - for communication
from the µP to the TDA7705), master input/slave output (MISO - for communication from the
TDA7705 to the µP), chip select (CS). CLK is generated by the master device and is used
for synchronization. MOSI and MISO are the data lines. The CS line is unique for each
device in an SPI bus. The µP pulls low the TDA7705 CS line to select it for communication.
The protocol does not foresee any transmission acknowledgement.
The SPI protocol has four possible modes of operation as far as data latching is concerned:
