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CY62167EV30LL-45BVI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
CY62167EV30 MoBL
®
Document Number: 38-05446 Rev. *N Page 10 of 19
Figure 8. Write Cycle No. 2 (CE
1
or CE
2
Controlled)
[30, 31]
Switching Waveforms (continued)
t
HD
t
SD
t
PWE
t
HA
t
AW
t
SCE
t
WC
t
HZOE
DATA IN VALID
t
BW
t
SA
NOTE 32
CE
1
ADDRESS
CE
2
WE
DATA I/O
OE
BHE/BLE
Notes
30. The internal write time of the memory is defined by the overlap of WE
, CE
1
= V
IL
, BHE or BLE or both = V
IL
, and CE
2
= V
IH
. All signals must be ACTIVE to initiate a
write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing must refer to the edge of the signal that terminates the write.
31. If CE
1
goes HIGH and CE
2
goes LOW simultaneously with WE = V
IH
, the output remains in a high impedance state.
32. During this period the I/Os are in output state. Do not apply input signals.
CY62167EV30 MoBL
®
Document Number: 38-05446 Rev. *N Page 11 of 19
Figure 9. Write Cycle No. 3 (WE controlled, OE LOW)
[33]
Figure 10. Write Cycle No. 4 (BHE/BLE controlled, OE LOW)
[33]
Switching Waveforms (continued)
DATA IN VALID
t
HD
t
SD
t
LZWE
t
PWE
t
SA
t
HA
t
AW
t
SCE
t
WC
t
HZWE
t
BW
NOTE 34
CE
1
ADDRESS
CE
2
WE
DATA I/O
BHE
/BLE
t
HD
t
SD
t
SA
t
HA
t
AW
t
WC
DATA IN VALID
t
BW
t
SCE
t
PWE
NOTE 34
CE
1
ADDRESS
CE
2
WE
DATA I/O
BHE
/BLE
Notes
33. If CE
1
goes HIGH and CE
2
goes LOW simultaneously with WE = V
IH
, the output remains in a high impedance state.
34. During this period the I/Os are in output state. Do not apply input signals.
CY62167EV30 MoBL
®
Document Number: 38-05446 Rev. *N Page 12 of 19
Truth Table
CE
1
CE
2
WE OE BHE BLE Inputs/Outputs Mode Power
HX
[35]
XXX
[35]
X
[35]
High Z Deselect/Power-down Standby (I
SB
)
X
[35]
LXXX
[35]
X
[35]
High Z Deselect/Power-down Standby (I
SB
)
X
[35]
X
[35]
X X H H High Z Deselect/Power-down Standby (I
SB
)
L H H L L L Data Out (I/O
0
–I/O
15
) Read Active (I
CC
)
L H H L H L Data Out (I/O
0
–I/O
7
);
High Z (I/O
8
–I/O
15
)
Read Active (I
CC
)
LHHLLHHigh Z (I/O
0
–I/O
7
);
Data Out (I/O
8
–I/O
15
)
Read Active (I
CC
)
L H H H L H High Z Output disabled Active (I
CC
)
LHHHHLHigh Z Output disabled Active (I
CC
)
L H H H L L High Z Output disabled Active (I
CC
)
L H L X L L Data In (I/O
0
–I/O
15
) Write Active (I
CC
)
L H L X H L Data In (I/O
0
–I/O
7
);
High Z (I/O
8
–I/O
15
)
Write Active (I
CC
)
LHLXLHHigh Z (I/O
0
–I/O
7
);
Data In (I/O
8
–I/O
15
)
Write Active (I
CC
)
Note
35. The ‘X’ (Don’t care) state for the chip enables and Byte enables in the truth table refer to the logic state (either HIGH or LOW). Intermediate voltage levels on these
pins is not permitted.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

CY62167EV30LL-45BVI

Mfr. #:
Buy CY62167EV30LL-45BVI
Manufacturer:
Cypress Semiconductor
Description:
SRAM 16Mb 3V 45ns 1M x 16 LP SRAM
Lifecycle:
New from this manufacturer.
Delivery:
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