FEDL610Q435-䋰2
LAPIS Semiconductor
ML610Q435/ML610Q436
29/35
AC CHARACTERISTICS (Synchronous Serial Port)
(V
DD
= 1.3 to 3.6V, AV
DD
= 2.2 to 3.6V, V
SS
= AV
SS
= 0V, Ta = 20 to +70qC, unless otherwise specified)
Rating
Parameter Symbol Condition
Min. Typ. Max.
Unit
When RC oscillation is active*
2
(V
DD
= 1.3 to 3.6V)
10
Ps
SCLK input cycle
(slave mode)
t
SCYC
When high-speed oscillation is
active*
3
(V
DD
= 1.8 to 3.6V)
1
Ps
SCLK output cycle
(master mode)
t
SCYC
SCLK*
1
s
When RC oscillation is active*
2
(V
DD
= 1.3 to 3.6V)
4
Ps
SCLK input pulse width
(slave mode)
t
SW
When high-speed oscillation is
active*
3
(V
DD
= 1.8 to 3.6V)
0.4
Ps
SCLK output pulse width
(master mode)
t
SW
SCLK*
1
u0.4
SCLK*
1
u0.5
SCLK*
1
u0.6
s
When RC oscillation is active*
2
(V
DD
=
1.3 to 3.6V)
500
SOUT output delay time
(slave mode)
t
SD
When high-speed oscillation is
active*
3
(V
DD
= 1.8 to 3.6V)
240
ns
When RC oscillation is active*
2
(V
DD
=
1.3 to 3.6V)
500
SOUT output delay time
(master mode)
t
SD
When high-speed oscillation is
active*
3
(V
DD
= 1.8 to 3.6V)
240
ns
SIN input
setup time
(slave mode)
t
SS
80 ns
When RC oscillation is active*
2
(V
DD
=
1.3 to 3.6V)
500
SIN input
setup time
(master mode)
t
SS
When high-speed oscillation is
active*
3
(V
DD
= 1.8 to 3.6V)
240
ns
When RC oscillation is active*
2
(V
DD
=
1.3 to 3.6V)
300
SIN input
hold time
t
SH
When high-speed oscillation is
active*
3
(V
DD
= 1.8 to 3.6V)
80
ns
*
1
: Clock period selected with S0CK3–0 of the serial port 0 mode register (SIO0MOD1)
*
2
: When RC oscillation is selected with OSCM1–0 of the frequency control register (FCON0)
*
3
: When Crystal/ceramic oscillation, built-in PLL oscillation, or external clock input is selected with OSCM1–0 of the frequency
control register (FCON0)
t
SD
SCLK0*
SIN0*
SOUT0*
*: Indicates the secondar
function of the
ort.
t
SD
t
SS
t
SH
t
SW
t
SW
t
SCYC
