__________Applications Information
Power-On Reset
At power-up, the internal power-on reset circuitry sets
INT high and puts the device in normal operation/exter-
nal clock mode. This state is selected to keep the inter-
nal clock from loading the external clock driver when
the part is used in external clock mode.
Internal or External Reference
The MAX196/MAX198 can operate with either an inter-
nal or external reference. An external reference can be
connected to either the REF pin or the REFADJ pin
(Figure 9).
To use the REF input directly, disable the internal buffer
by tying REFADJ to V
DD
. Using the REFADJ input elimi-
nates the need to buffer the reference externally. When
the reference is applied at REFADJ, bypass REFADJ with
a 0.01µF capacitor to AGND.
The REFADJ internal buffer gain is trimmed to 1.6384 to
provide 4.096V at the REF pin from a 2.5V reference.
Internal Reference
The internally trimmed 2.50V reference is gained
through the REFADJ buffer to provide 4.096V at REF.
Bypass the REF pin with a 4.7µF capacitor to AGND
and the REFADJ pin with a 0.01µF capacitor to AGND.
The internal reference voltage is adjustable to ±1.5%
(±65 LSBs) with the reference-adjust circuit of Figure 1.
External Reference
At REF and REFADJ, the input impedance is a mini-
mum of 10kfor DC currents. During conversions, an
external reference at REF must be able to deliver
400µA DC load currents, and must have an output
impedance of 10or less. If the reference has higher
output impedance or is noisy, bypass it close to the
REF pin with a 4.7µF capacitor to AGND.
With an external reference voltage of less than 4.096V
at the REF pin or less than 2.5V at the REFADJ pin, the
increase in the ratio of the RMS noise to the LSB value
(FS / 4096) results in performance degradation (loss of
effective bits).
Power-Down Mode
To save power, you can put the converter into low-
current shutdown mode between conversions. Two
programmable power-down modes are available:
STBYPD and FULLPD. Select STBYPD or FULLPD by
programming PD0 and PD1 in the input control byte.
When power-down is asserted, it becomes effective
only after the end of conversion. In all power-down
modes, the interface remains active and conversion
MAX196/MAX198
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
______________________________________________________________________________________ 13
REF
10k
2.5V
26
4.096V
4.7µF
C
REF
0.01µF
25REFADJ
A
V
= 1.638
MAX196
MAX198
Figure 9a. Internal Reference
REF
10k
2.5V
26
4.7µF
C
REF
2.5V
25REFADJ
A
V
= 1.638
0.01µF
MAX196
MAX198
4.096V
Figure 9c. The external reference overdrives the internal refer-
ence.
REF
V
DD
10k
2.5V
26
4.096V
4.7µF
C
REF
25REFADJ
A
V
= 1.638
MAX196
MAX198
Figure 9b. External Reference, Reference at REF
MAX196/MAX198
results may be read. Input overvoltage protection is
active in all power-down modes. The device returns to
normal operation on the first WR falling edge during
write operation.
Choosing Power-Down Modes
The bandgap reference and reference buffer remain
active in STBYPD mode, maintaining the voltage on the
4.7µF capacitor at the REF pin. This is a “DC” state that
does not degrade after power-down of any duration.
Therefore, you can use any sampling rate with this
mode, without regard to start-up delays.
However, in FULLPD mode, only the bandgap refer-
ence is active. Connect a 33µF capacitor between REF
and AGND to maintain the reference voltage between
conversions and to reduce transients when the buffer is
enabled and disabled. Throughput rates down to 1ksps
can be achieved without allotting extra acquisition time
for reference recovery prior to conversion. This allows
conversion to begin immediately after power-down
ends. If the discharge of the REF capacitor during
FULLPD exceeds the desired limits for accuracy (less
than a fraction of an LSB), run a STBYPD power-down
cycle prior to starting conversions. Take into account
that the reference buffer recharges the bypass capaci-
tor at an 80mV/ms slew rate, and add 50µs for settling
time. Throughput rates of 10ksps offer typical supply
currents of 470µA, using the recommended 33µF
capacitor value.
Auto-Shutdown
Selecting STBYPD on every conversion automatically
shuts the MAX196/MAX198 down after each conversion
without requiring any start-up time on the next conversion.
Transfer Function
Output data coding for the MAX196/MAX198 is binary
in unipolar mode with 1LSB = (FS / 4096) and twos-
complement binary in bipolar mode with 1LSB = [(2 x
|
FS
|
) / 4096]. Code transitions occur halfway between
successive-integer LSB values. Figures 10 and 11
show the input/output (I/O) transfer functions for unipo-
lar and bipolar operations, respectively. For full-scale
(FS) values, refer to Table 1.
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
14 ______________________________________________________________________________________
OUTPUT CODE
INPUT VOLTAGE (LSB)
0
FS
FS -
3
/
2
LSB
1 LSB =
FULL-SCALE
TRANSITION
123
11... 111
11... 110
11... 101
00... 011
00... 010
00... 001
00... 000
FS
4096
Figure 10. Unipolar Transfer Function
OUTPUT CODE
INPUT VOLTAGE (LSB)
0V +FS - 1 LSB
1 LSB =
-FS
011... 111
011... 110
000... 001
000... 000
111... 111
100... 010
100... 001
100... 000
2FS
4096
Figure 11. Bipolar Transfer Function
Layout, Grounding, and Bypassing
Careful printed circuit board layout is essential for best
system performance. For best performance, use a
ground plane. To reduce crosstalk and noise injection,
keep analog and digital signals separate. Digital
ground lines can run between digital signal lines to
minimize interference. Connect analog grounds and
DGND in a star configuration to AGND. For noise-free
operation, ensure the ground return from AGND to the
supply ground is low impedance and as short as possi-
ble. Connect the logic grounds directly to the supply
ground. Bypass V
DD
with 0.1µF and 4.7µF capacitors
to AGND to minimize high- and low-frequency fluctua-
tions. If the supply is excessively noisy, connect a 5
resistor between the supply and V
DD
, as shown in
Figure 12.
MAX196/MAX198
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
______________________________________________________________________________________ 15
V
DD
GND
DGND
DGNDAGND
+5V
+5V
SUPPLY
R* = 5
DIGITAL
CIRCUITRY
4.7µF
0.1µF
MAX196
MAX198
**
* OPTIONAL
** CONNECT AGND AND DGND WITH A GROUND PLANE OR A SHORT TRACE
Figure 12. Power-Supply Grounding Connection
_________________________________________________________Functional Diagram
T/H
THREE-STATE, BIDIRECTIONAL
I/O INTERFACE
12
10k
12
8
CHARGE REDISTRIBUTION
12-BIT DAC
CLOCK
SIGNAL
CONDITIONING
BLOCK
&
OVERVOLTAGE
TOLERANT
MUX
CONTROL LOGIC
&
LATCHES
REF REFADJ
+2.5V
REFERENCE
D0–D11
12-BIT DATA BUS
CH5
CH4
CH3
CH2
CH1
CH0
CLK
CS
WR
RD
INT
V
DD
AGND
DGND
MAX196
MAX198
A
V
= 
1.638
COMP
SUCCESSIVE-
APPROXIMATION
REGISTER

MAX198BCWI+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Analog to Digital Converters - ADC 12-Bit 8Ch 100ksps 4.18V Precision ADC
Lifecycle:
New from this manufacturer.
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