MAX196/MAX198
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
_______________________________________________________________________________________ 5
Note 1: Accuracy specifications tested at V
DD
= 5.0V. Performance at power-supply tolerance limits guaranteed by Power-Supply
Rejection test. Tested for the ±10V (MAX196) and ±4.096V (MAX198) input ranges.
Note 2: External reference: V
REF
= 4.096V, offset error nulled, ideal last code transition = FS - 3/2LSB.
Note 3: Ground “on” channel; sine wave applied to all “off” channels.
Note 4: Maximum full-power input frequency for 1LSB error with 10ns jitter = 3kHz.
Note 5: Guaranteed by design. Not tested.
Note 6: Use static loads only.
Note 7: Tested using internal reference.
Note 8: PSRR measured at full-scale.
Note 9: External acquisition timing: starts at data valid at ACQMOD = low control byte; ends at rising edge of WR
with ACQMOD
= high control byte.
Note 10: Not subject to production testing. Provided for design guidance only.
Note 11: All input control signals specified with t
R
= t
F
= 5ns from a voltage level of 0.8V to 2.4V.
Note 12: t
DO
is measured with the load circuits of Figure 2 and defined as the time required for an output to cross 0.8V or 2.4V.
Note 13: t
TR
is defined as the time required for the data lines to change by 0.5V.
TIMING CHARACTERISTICS
(V
DD
= 5V ±5%; unipolar/bipolar range; external reference mode, V
REF
= 4.096V; 4.7µF at REF pin; external clock, f
CLK
= 2.0MHz
with 50% duty cycle; T
A
= T
MIN
to T
MAX
; unless otherwise noted.)
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 5V ±5%; unipolar/bipolar range; external reference mode, V
REF
= 4.096V; 4.7µF at REF pin; external clock, f
CLK
= 2.0MHz
with 50% duty cycle; T
A
= T
MIN
to T
MAX
; unless otherwise noted. Typical values are at T
A
= +25°C.)
Three-State Output Capacitance C
OUT
15 pF(Note 5)
Output High Voltage V
OH
V
DD
- 1 VV
DD
= 4.75V, I
SOURCE
= 1mA
Output Low Voltage V
OL
0.4 VV
DD
= 4.75V, I
SINK
= 1.6mA
PARAMETER SYMBOL MIN TYP MAX UNITSCONDITIONS
DIGITAL OUTPUTS (D11–D0, INT)
RD Low to Output Data Valid
t
DO
120 nsFigure 2, C
L
= 100pF (Note 12)
Data Valid to WR Setup
Data Valid to WR Hold t
DH
0 ns
t
DS
60 ns
CLK to WR Setup Time
CLK to WR Hold Time t
CWH
50 ns
t
CWS
100 ns
CS to RD Setup Time
CS to RD Hold Time t
CSRH
0 ns
t
CSRS
0 ns
CS to WR Setup Time
CS to WR Hold Time t
CSWH
0 ns
t
CSWS
0 ns
WR Pulse Width t
WR
80 ns
PARAMETER SYMBOL MIN TYP MAX UNITS
CS Pulse Width t
CS
80 ns
RD Low to INT High Delay
t
INT1
120 ns
RD High to Output Disable
t
TR
CONDITIONS
70 ns(Note 13)
