MAX196/MAX198
Multirange, Single +5V, 12-Bit DAS
with 12-Bit Bus Interface
8 _______________________________________________________________________________________
Acquisition time is calculated as follows:
For 0V to V
REF
: t
AZ
= 9 x (R
S
+ R
IN
) x 16pF
For 0V to V
REF
/2: t
AZ
= 9 x (R
S
+ R
IN
) x 32pF
where R
IN
= 7kΩ and t
AZ
is never less than 2µs (0V to
V
REF
range) or 3µs (0V to V
REF
/2 range).
In the external acquisition control mode (D5 = 1), the
T/H enters its tracking mode on the first WR rising edge
and enters its hold mode when it detects the second
WR rising edge with D5 = 0 (see
External Acquisition
section).
Input Bandwidth
The ADC’s input tracking circuitry has a 5MHz small-
signal bandwidth. When using the internal acquisition
mode with an external clock frequency of 2MHz, a
100ksps throughput rate can be achieved. It is possible
to digitize high-speed transient events and measure
periodic signals with bandwidths exceeding the ADC’s
sampling rate by using undersampling techniques. To
avoid high-frequency signals being aliased into the fre-
quency band of interest, anti-alias filtering is recom-
mended (MAX274/MAX275 continuous-time filters).
Input Range and Protection
Figure 4 shows the equivalent input circuit. The full-
scale input voltage depends on the voltage at the refer-
ence (V
REF
). The MAX196 uses a scaling factor, which
allows input voltage ranges of ±10V, ±5V, 0V to +10V,
or 0V to +5V with a 4.096V voltage reference (Table 1).
Program the desired range by setting the appropriate
control bits (D3, D4) in the control byte (Tables 2 and
3). The MAX198 does not use a scaling factor, so its
input voltage range directly corresponds with the refer-
ence voltage. It can be programmed for input voltages
of ±V
REF
, ±V
REF
/2, 0V to V
REF
, or 0V to V
REF
/2 (Table
3). When an external reference is applied at REFADJ,
the voltage at REF is given by V
REF
= 1.6384 x V
REFADJ
(2.4V < V
REF
< 4.18V).
The input channels are overvoltage protected to
±16.5V. This protection is active even if the device is in
power-down mode.
Even with V
DD
= 0V, the input resistive network provides
current-limiting that adequately protects the device.
Digital Interface
Input data (control byte) and output data are multi-
plexed on a three-state parallel interface. This parallel
I/O can easily be interfaced with a µP. CS, WR, and RD
control the write and read operations. CS is the stan-
dard chip-select signal, which enables a µP to address
the MAX196/MAX198 as an I/O port. When high, it dis-
ables the WR and RD inputs and forces the interface
into a high-Z state.
DGND
V
DD
REF
REFADJ
INT
CH5
CH4
CH3
CH2
CH1
CH0
AGND
28
27
23
4.7µF4.7µF
0.01µF 0.01µF
+5V
OUTPUT STATUS
22
24
21
20
19
18
17
16
1
25
µP
CONTROL
INPUTS
26
2
3
4
CLK
RD
WR
CS
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
100pF
µP DATA BUS
15
5
6
7
8
9
10
11
12
13
14
ANALOG
INPUTS
MAX196
MAX198
Figure 3. Operational Diagram
5.12k
R2
R1
CH_
S1
S2
S3
S4
BIPOLAR
UNIPOLAR
VOLTAGE
REFERENCE
T/H
OUT
HOLDTRACK
TRACKHOLD
OFF
ON
C
HOLD
S1 = BIPOLAR/UNIPOLAR SWITCH
S2 = INPUT MUX SWITCH
S3, S4 = T/H SWITCH
R1 = 12.5kΩ (MAX196) OR 5.12kΩ (MAX198)
R2 = 8.67kΩ (MAX196) OR ∞ (MAX198)
Figure 4. Equivalent Input Circuit
RANGE (V)
ZERO SCALE
(V) -FULL SCALE +FULL SCALE
0 to +5 0 — V
REF
x 1.2207
0 to +10 0 — V
REF
x 2.4414
±5 — -V
REF
x 1.2207 V
REF
x 1.2207
±10 — -V
REF
x 2.4414 V
REF
x 2.4414
Table 1. Full Scale and Zero Scale
(MAX196 only)
