L9954LXP Functional description of the SPI
Doc ID 16186 Rev 3 25/35
4.5 Serial Clock (CLK)
The CLK input is used to synchronize the input and output serial bit streams. The data input
(DI) is sampled at the rising edge of the CLK and the data output (DO) changes with the
falling edge of the CLK signal.
4.6 Input Data Register
The device has two input registers. The first bit (bit 0) at the DI input is used to select one of
the two input registers. All bits are first shifted into an input shift register. After the rising
edge of CSN the contents of the input shift register is written to the selected input data
register only if a frame of exact 24 data bits are detected. Depending on bit 0 the contents of
the selected status register is transferred to DO during the current communication frame. Bit
1-17 controls the behavior of the corresponding driver.
If bit 23 is zero, the device goes into the standby mode. The bits 18 and 19 are used to
control the current monitor multiplexer. Bit 22 is used to reset all status bits in both status
registers. The bits in the status registers is cleared after the current communication frame
(rising edge of CSN).
4.7 Status register
This devices uses two status registers to store and to monitor the state of the device. No
error bit (bit 0) is used as a fault bit and is a logical-NOR combination of bits 1-22 in both
status registers. The state of this bit can be polled by the microcontroller without the need of
a full SPI communication cycle. If one of the over-current bits is set, the corresponding driver
is disabled. If the over-current recovery bit of the output is not set the microcontroller has to
clear the over-current bit to enable the driver. If the thermal shutdown bit is set, all drivers
goes into a high impedance state. Again the microcontroller has to clear the bit to enable the
drivers.
Functional description of the SPI L9954LXP
26/35 Doc ID 16186 Rev 3
4.8 SPI - input data and status registers
Table 18. SPI - input data and status registers 0
Bit
Input register 0 (write) Status register 0 (read)
Name Comment Name Comment
23 Enable bit
If enable bit is set the
device switches in active
mode. If enable bit is
cleared the device goes
into standby mode and all
bits are cleared. After
power-on reset device
starts in standby mode.
Always 1
A broken V
CC
-or SPI
connection of the L9954LXP
can be detected by the
microcontroller, because all 24
bits low or high is not a valid
frame.
22 Reset bit
If reset bit is set both
status registers are
cleared after rising edge of
CSN input.
V
S
overvoltage
In case of an overvoltage or
undervoltage event the
corresponding bit is set and
the outputs are deactivated. If
V
S
voltage recovers to normal
operating conditions outputs
are reactivated automatically
(if bit 20 of status register 0 is
not set).
21
OC recovery
duty cycle
This bit defines in
combination with the over-
current recovery bit (input
register 1) the duty cycle
in overcurrent condition of
an activated driver.
V
S
undervoltage
0: 12% 1: 25%
20
Overvoltage/
undervoltage
recovery
disable
If this bit is set the
microcontroller has to
clear the status register
after under voltage /
overvoltage event to
enable the outputs.
Thermal
shutdown
In case of a thermal shutdown
all outputs are switched off.
The microcontroller has to
clear the TSD bit by setting the
Reset Bit to reactivate the
outputs.
19
Current monitor
select bits
Depending on
combination of bit 18 and
19 the current image
(1/10.000) of the selected
HS-output is multiplexed
to the CM output:
Temperature
warning
The TW bit can be used for
thermal management by the
microcontroller to avoid a
thermal shutdown. The
microcontroller has to clear the
TW bit.
18
Bit
19
Bit
18
Output
Not ready bit
After switching the device from
standby mode to active mode
an internal timer is started to
allow charge pump to settle
before the outputs can be
activated. This bit is cleared
automatically after start up
time has finished. Since this bit
is controlled by internal clock it
can be used for synchronizing
testing events (e.g. measuring
filter times).
00 OUT6
10 OUT1
01 OUT4
11 OUT5
L9954LXP Functional description of the SPI
Doc ID 16186 Rev 3 27/35
17
OUT6 – HS
on/off
If a bit is set the selected
output driver is switched
on. If the corresponding
PWM enable bit is set
(input register 1) the driver
is only activated if PWM1
(PWM2) input signal is
high. The outputs of
OUT1-OUT3 are half
bridges. If the bits of HS-
and LS-driver of the same
half bridge are set, the
internal logic prevents that
both drivers of this output
stage can be switched on
simultaneously in order to
avoid a high internal
current from V
S
to GND.
OUT6 – HS
over-current
In case of an over-current
event the corresponding status
bit is set and the output driver
is disabled. If the over-current
recovery enable bit is set
(input register 1) the output is
automatically reactivated after
a delay time resulting in a
PWM modulated current with a
programmable duty cycle (bit
21).
If the over-current recovery bit
is not set the microcontroller
has to clear the over-current
bit (reset bit) to reactivate the
output driver.
16 x (don’t care) 0
15
OUT5 – HS
on/off
OUT5 – HS
over-current
14
OUT4 – HS
on/off
OUT4 – HS
over-current
13 x (don’t care) 0
12 x (don’t care) 0
11 x (don’t care) 0
10 x (don’t care) 0
9 x (don’t care) 0
8 x (don’t care) 0
7 x (don’t care) 0
6
OUT3 – HS
on/off
OUT3 – HS
over-current
5
OUT3 – LS
on/off
OUT3 – LS
over-current
4
OUT2 – HS
on/off
OUT2 – HS
over-current
3
OUT2 – LS
on/off
OUT2 – LS
over-current
2
OUT1 – HS
on/off
OUT1 – HS
over-current
1
OUT1 – LS
on/off
OUT1 – LS
over-current
0 0 No error bit
A logical NOR-combination of
all bits 1 to 22 in both status
registers.
Table 18. SPI - input data and status registers 0 (continued)
Bit
Input register 0 (write) Status register 0 (read)
Name Comment Name Comment

L9954LXPTR

Mfr. #:
Manufacturer:
STMicroelectronics
Description:
Motor / Motion / Ignition Controllers & Drivers Door Actuator Driver 0.75A 1600mOhm
Lifecycle:
New from this manufacturer.
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