Data Sheet ADuCM320i
Table 5. SPI Master Mode Timing (Phase Mode = 0)
Parameter Description Min Typ Max Unit
t
SL
SCLK low pulse width (SPIDIV + 1) × t
HCLK
/2 ns
t
SH
SCLK high pulse width (SPIDIV + 1) × t
HCLK
/2 ns
t
DAV
Data output valid after SCLK edge 0 3 ns
t
DOSU
Data output setup before SCLK edge ½ SCLK ns
t
DSU
Data input setup time before SCLK edge SCLK ns
t
DHD
Data input hold time after SCLK edge SCLK ns
t
DF
Data output fall time 25 ns
t
DR
Data output rise time 25 ns
t
SR
SCLK rise time 20 ns
t
SF
SCLK fall time 20 ns
SCLK
(POLARITY = 0)
SCLK
(POLARITY = 1)
t
SH
t
SL
t
SR
t
SF
MOSI MSB BIT 6 TO BIT 1 LSB
MISO MSB IN BIT 6 TO BIT 1 LSB IN
t
DR
t
DF
t
DAV
t
DOSU
t
DSU
t
DHD
13422-004
F
igure 4. SPI Master Mode Timing (Phase Mode = 0)
Rev. 0 | Page 13 of 26
