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EVAL-ADUCM320IQSPZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27
Data Sheet ADuCM320i
Pin No. Mnemonic Type
1
Description
L10 AIN8/P4.2 AI/I/O Analog Input 8 (AIN8).
Digital I/O Port 4.2 (P4.2).
K10 AIN9/P4.3 AI/I/O Analog Input 9 (AIN9).
Digital I/O Port 4.3 (P4.3).
J10
AIN10
AI
Analog Input 10.
J11 AIN11/BUF_VREF2V5 AI/AO Analog Input 11 (AIN11).
Buffered 2.5 V Bias (BUF_VREF2V5). The maximum load is 1.2 mA. Connect
BUF_VREF2V5 to AGNDx via a 100 nF capacitor.
H10 AIN12/P4.4 AI/I/O Analog Input 12 (AIN12).
Digital I/O Port 4.4 (P4.4).
G10
AIN13/P4.5
AI/I/O
Analog Input 13 (AIN13).
Digital I/O Port 4.5 (P4.5).
H9 AIN14/P4.6 AI/I/O Analog Input 14 (AIN14).
Digital I/O Port 4.6 (P4.6).
G9 AIN15/P4.7 AI/I/O Analog Input 15 (AIN15).
Digital I/O Port 4.7 (P4.7).
L5 VDAC0/P5.3 AO/I/O Voltage DAC0 Output (VDAC0).
Digital I/O Port 5.3 (P5.3).
K5 VDAC1 AO Voltage DAC1 Output.
L4 VDAC2/P3.7/PLAO[29] AO/I/O Voltage DAC2 Output (VDAC2).
Digital I/O Port 3.7 (P3.7).
Output of PLA Element 29 (PLAO[29]).
K4 VDAC3/P5.0 AO/I/O Voltage DAC3 Output (VDAC3).
Digital I/O Port 5.0 (P5.0).
J4 VDAC4 AO Voltage DAC4 Output (VDAC4).
L3 VDAC5 AO Voltage DAC5 Output (VDAC5).
K3 VDAC6/P5.1 AO/I/O Voltage DAC6 Output (VDAC6).
Digital I/O Port 5.1 (P5.1).
J3 VDAC7/P5.2 AO/I/O Voltage DAC7 Output (VDAC7).
Digital I/O Port 5.2 (P5.2).
A2 IDAC0 AO IDAC0. 0 mA to 150 mA full-scale output.
A3 PVDD0 S Power for IDAC0.
B4 CDAMP0 AI Damping Capacitor 0. Connect a damping capacitor from this pin to PVDD0.
A10 IDAC1 AO IDAC1. 0 mA to 150 mA full-scale output.
A9 PVDD1 S Power for IDAC1.
B8 CDAMP1 AI Damping Capacitor 1. Connect a damping capacitor from this pin to PVDD1.
A5 IDAC2 AO IDAC2. 0 mA to 150 mA full-scale output.
A4 PVDD2 S Power for IDAC2.
B5 CDAMP2 AI Damping Capacitor 2. Connect a damping capacitor from this pin to PVDD2.
A7 IDAC3 AO IDAC3. 0 mA to 150 mA full-scale output.
A8 PVDD3 S Power for IDAC3.
B7 CDAMP3 AI Damping Capacitor 3. Connect a damping capacitor from this pin to PVDD3.
B6 PGND S Power Supply Ground for IDACs.
A6 PGND S Power Supply Ground for IDACs.
A1 IDAC_TST AI/AO Pin for IDAC Test Purposes. Leave IDAC_TST unconnected.
L2 DVDD_1V8 AO 1.8 V Digital Supply. A 470 nF capacitor to DGND1 must be connected to this
pin to stabilize the internal 1.8 V regulator that supplies flash memory and the
ARM Cortex-M3 processor.
K2 DVDD_2V5 AO 2.5 V Digital Supply. A 470 nF capacitor to IOGND3 must be connected to this
pin to stabilize the internal 2.5 V regulator that supplies the analog digital
control.
Rev. 0 | Page 21 of 26
ADuCM320i Data Sheet
Pin No. Mnemonic Type
1
Description
F9 AVDD_REG0 AO Analog Regulator 0 Supply. A 470 nF capacitor to AGND4 must be connected to
this pin to stabilize the internal 2.5 V regulator that supplies the ADC.
F10 AVDD_REG1 AO Analog Regulator 1 Supply. Output of 2.5 V on-chip LDO regulator. A 470 nF
capacitor to AGND4 must be connected to this pin. This regulator supplies the
IDACs.
L1 DGND1 S Digital Ground 1 for DVDD_1V8.
D10 DGND2 S Digital Ground 2. Connect to DGND1.
B1 IOVDD1 S 3.3 V GPIO Supply.
D11 IOVDD2 S 3.3 V GPIO Supply and Interdie Communications.
J1 IOVDD3 S 3.3 V GPIO Supply.
C1 IOGND1 S Ground for IOVDD1.
E11 IOGND2 S Ground for IOVDD2.
K1 IOGND3 S Ground for IOVDD3 and Interdie Communications.
J5 AGND1 S Analog Ground for VDD1.
K7 AGND2 S ESD Ground for Pad Ring.
L7 AGND3 S Ground for AVDD3.
H11 AGND4 S Ground for AVDD4, AVDD_REG0, and AVDD_REG1.
K6 VDD1 S 3.3 V Supply for Digital Die.
L6 AVDD3 S VDAC and IDAC Supply (3.3 V).
G11 AVDD4 S ADC Supply (3.3 V).
L11 ADC_REFN AO/A Negative Decoupling Capacitor Connection for ADC Reference Buffer. Connect
this pin to AGND4.
K11 ADC_REFP AO/A Positive Decoupling Capacitor Connection for ADC Reference Buffer. Connect
this pin to a 4.7 µF capacitor to the ADC_REFN pin. ADC_REFP can be overdriven
by an external reference.
H2 XTALO O Output from the Crystal Oscillator Inverter. When not using an external crystal,
leave XTALO unconnected.
J2 XTALI I Input to the Crystal Oscillator Inverter and Input to the Internal Clock Generator
Circuits. When not using an external crystal, connect XTALI to DGNDx.
1
I is digital input, O is digital output, S is supply, AI is analog input, and AO is analog output.
Rev. 0 | Page 22 of 26
Data Sheet ADuCM320i
Rev. 0 | Page 23 of 26
TYPICAL PERFORMANCE CHARACTERISTICS
25000
30000
35000
40000
45000
50000
–60 –40 –20 0 20 40 60 80 100 120
ADC CODE (LSB 16)
TEMPERATURE (°C)
DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 4
DEVICE 5
13422-009
Figure 9. Typical Temperature Measurement (ADC Code) vs. Internal
Temperature (V
DD
= 3.3 V, 50 kSPS)
–10
0
10
20
30
40
50
60
70
80
90
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
PIN CURRENT (µA)
PIN VOLTAGE (V)
MAX PULL-UP
MIN PULL-UP
MIN PULL-DOWN
MAX PULL-DOWN
13422-010
Figure 10. Typical Pull-Up/Pull-Down Pin Current vs. Pin Voltage
(V
DD
= 3.3 V, 25°C)
0
50
100
150
200
250
300
350
0 25 50 75 100 125 150
IDAC HEADROOM (mV)
IDAC OUTPUT CURRENT (mA)
IDAC2
IDAC3
IDAC0
IDAC1
13422-011
Figure
11. Typical IDAC Headroom vs. IDAC Output Current
–70
–60
–50
–40
–30
–20
–10
0
100 1k 10k 100k
PVDD AC PSRR (dB)
FREQUENCY (Hz)
IDAC0
IDAC1
IDAC2
IDAC3
13422-012
Figure 12. Typical PVDD AC PSRR vs. Frequency
0
0.5
1.0
1.5
2.0
2.5
3.0
2
6101416
0
4812
OUTPUT VOLTAGE (V)
LOAD CURRENT (mA)
V
OH
MAX
V
OH
MIN
V
OL
MIN
V
OL
MAX
13422-013
Fig
ure 13. Typical Output Voltage vs. Load Current
TIME (Not to Scale)
3.6
40ms min
VDD1 (V)
VDD1 MUST BE ABOVE 3V
FOR AT LEAST 40ms TO
COMPLETE POR
AFTER 40ms VDD1 MUST
STAY ABOVE 2.9V INCLUDING
NOISE EXCURSIONS
3.0
2.9
13422-014
Fi
gure 14. VDD1 Power-On Requirements
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27

EVAL-ADUCM320IQSPZ

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Manufacturer:
Analog Devices Inc.
Description:
Development Boards & Kits - ARM ADUCM320i Quick Start Plus Dev. Kit
Lifecycle:
New from this manufacturer.
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