ADuCM320i Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
A
B
C
D
E
F
G
H
J
K
L
2 3 4 5 6 7 8 9 10 11
IDAC_
TST
IDAC0
IDAC 2
IOVDD1
DIGITAL
IOGND1
P3.3/
PRTADDR3/
PLAI[15]
P0.0/
SCLK0/
PLAI[0]
CDAMP0
CDAMP2 CDAMP3
CDAMP1
IDAC1 IREFIDAC 3PGND
DGND2
SWCLK
AIN15/
P4.7
AIN14/
P4.6
AIN12/
P4.4
AIN11/
BUF_
VREF2V5
AIN10
AIN7
AIN2
AIN1
AIN0AGND1
VDAC4
VDAC7/
P5.2
VDAC6/
P5.1
XTALI
IOVDD3
IOGND3
VDAC3/
P5.0
VDAC1 VDD1
AVDD3
AGND2
AGND3
AIN3
AIN4
AIN6
AIN5
AIN9/
P4.3
AIN8/
P4.2
VDAC0/
P5.3
VDAC2 /
P3.7/
PLAO[29]
VDAC5DGND1
AGND4
AIN13/
P4.5
AVDD4
SWDIO IOGND2
IOVDD2
PGND
PVDD0
1DDVP3DDVP2DDVP
RESET
P1.0/SIN/
ECLKIN/
PLAI[4]
P1.2/
PWM0/
PLAI[6]
P1.1/SOUT/
PLACLK1/
PLAI[5]
P2.4/IRQ5/
ADCCONV/
PWM6/
PLAO[18]
P1.3/
PWM1/
PLAI[7]
P1.4/
PWM2/
SCLK1/
PLAO[10]
P1.5/
PWM3/
MISO1/
PLAO[11]
P1.6/
PWM4/
MOSI1/
PLAO[12]
P1.7/IRQ1/
PWM5/
CS1/
PLAO[13]
P2.0/IRQ2/
PWMTRIP/
PLACLK2/
PLAI[8]
P2.2/
IRQ4/POR/
CLKOUT/
PLAI[10]
P2.3/BM
P0.2/
MOSI0/
PLAI[2]
P0.5/
SDA0/
PLAO[3]
P2.6/
IRQ7/
PLAO[20]
P0.7/
SDA1/
PLAO[5]
P0.6/
SCL1/
PLAO[4]
P3.0/
PRTADDR0/
PLAI[12]
P3.1/
PRTADDR1/
PLAI[13]
P2.7/
IRQ8/
PLAO[21]
P3.5/
MCK/
PLAO[27]
XTALO
MDIO
P0.4/
SCL0/
PLAO[2]
P0.3/
IRQ0/CS0/
PLACLK0/
PLAI[3]
P0.1/
MISO0/
PLAI[1]
P3.2/
PRTADDR2/
PLAI[14]
P3.4/
PRTADDR4/
PLAO[26]
AVDD_
REG0
AVDD_
REG1
VRE F_1V2
ADC_
REFP
ADC_
REFN
DVDD_
2V5
DVDD_1V8
ADuCM320i
TOP VIEW
(Not to Scale)
IDAC
ANALOG
13422-008
F
igure 8. Pin Configuration
Table 10. Pin Function Descriptions
Pin No. Mnemonic Type
1
Description
B2
RESET
I Reset Input (Active Low). An internal pull-up resistor is included.
C2 P0.0/SCLK0/PLAI[0] I/O Digital I/O Port 0.0 (P0.0).
SPI0 Clock (SCLK0).
Input to PLA Element 0 (PLAI[0]).
D2 P0.1/MISO0/PLAI[1] I/O Digital I/O Port 0.1 (P0.1).
SPI0 Master Input, Slave Output (MISO0).
Input to PLA Element 1 (PLAI[1]).
D1 P0.2/MOSI0/PLAI[2] I/O Digital I/O Port 0.2 (P0.2).
SPI0 Master Output, Slave Input (MOSI0).
Input to PLA Element 2 (PLAI[2]).
E3 P0.3/IRQ0/CS0/PLACLK0/PLAI[3] I/O Digital I/O Port 0.3 (P0.3).
External Interrupt 0 (IRQ0).
SPI0 Chip Select 0 (CS0). When using SPI0, configure this pin as CS0.
PLA Clock 0 (PLACLK0).
Input to PLA Element 3 (PLAI[3]).
E2 P0.4/SCL0/PLAO[2] I/O Digital I/O Port 0.4 (P0.4).
I
2
C0 Serial Clock (SCL0).
Output of PLA Element 2 (PLAO[2]).
Rev. 0 | Page 18 of 26
Data Sheet ADuCM320i
Pin No. Mnemonic Type
1
Description
E1 P0.5/SDA0/PLAO[3] I/O Digital I/O Port 0.5 (P0.5).
I
2
C0 Serial Data (SDA0).
Output of PLA Element 3 (PLAO[3]).
F3 P0.6/SCL1/PLAO[4] I/O Digital I/O Port 0.6 (P0.6).
I
2
C1 Serial Clock (SCL1).
Output of PLA Element 4 (PLAO[4]).
F2 P0.7/SDA1/PLAO[5] I/O Digital I/O Port 0.7 (P0.7).
I
2
C1 Serial Data (SDA1).
Output of PLA Element 5 (PLAO[5]).
B9 P1.0/SIN/ECLKIN/PLAI[4] I/O Digital I/O Port 1.0 (P1.0).
UART Input (SIN).
External Input Clock (ECLKIN).
Input to PLA Element 4 (PLAI[4]).
B10 P1.1/SOUT/PLACLK1/PLAI[5] I/O Digital I/O Port 1.1 (P1.1).
UART Output (SOUT)
PLA Clock 1(PLACLK1).
Input to PLA Element 5 (PLAI[5]).
B11 P1.2/PWM0/PLAI[6] I/O Digital I/O Port 1.2 (P1.2).
PWM Output 0 (PWM0).
Input to PLA Element 6 (PLAI[6]).
C6 P1.3/PWM1/PLAI[7] I/O Digital I/O Port 1.3 (P1.3).
PWM Output 1 (PWM1).
Input to PLA Element 7 (PLAI[7]).
C7 P1.4/PWM2/SCLK1/PLAO[10] I/O Digital I/O Port 1.4 (P1.4).
PWM Output 2 (PWM2).
SPI1 Clock (SCLK1).
Output of PLA Element 10 (PLAO[10]).
C8 P1.5/PWM3/MISO1/PLAO[11] I/O Digital I/O Port 1.5 (P1.5).
PWM Output 3 (PWM3).
SPI1 Master Input, Slave Output (MISO1).
Output of PLA Element 11 (PLAO[11]).
C9 P1.6/PWM4/MOSI1/PLAO[12] I/O Digital I/O Port 1.6 (P1.6).
PWM Output 4 (PWM4).
SPI1 Master Output, Slave Input (MOSI1).
Output of PLA Element 12 (PLAO[12]).
C10 P1.7/IRQ1/PWM5/CS1/PLAO[13] I/O Digital I/O Port 1.7 (P1.7).
External Interrupt 1 (IRQ1).
PWM Output 5 (PWM5).
SPI1 Chip Select 1 (CS1). When using SPI1, configure this pin as CS1.
Output of PLA Element 13 (PLAO[13]).
C5 P2.0/IRQ2/PWMTRIP/PLACLK2/PLAI[8] I/O Digital I/O Port 2.0 (P2.0).
External Interrupt 2 (IRQ2).
PWM Trip (PWMTRIP).
PLA Input Clock 2 (PLACLK2).
Input to PLA Element 8 (PLAI[8]).
C4 P2.2/IRQ4/
POR
/CLKOUT/PLAI[10] I/O Digital I/O Port 2.2 (P2.2).
External Interrupt 4 (IRQ4).
Reset Output (
POR
).
Clock Output (CLKOUT).
Input to PLA Element 10 (PLAI[10]).
Rev. 0 | Page 19 of 26
ADuCM320i Data Sheet
Pin No. Mnemonic Type
1
Description
C3 P2.3/BM I/O Digital I/O Port 2.3 (P2.3).
Boot Mode (BM). This pin determines the start-up sequence after every reset.
Pull-up is enabled at power-up.
D9 P2.4/IRQ5/ADCCONV/PWM6/PLAO[18] I/O Digital I/O Port 2.4 (P2.4).
External Interrupt 5 (IRQ5).
External Input to Start ADC Conversions (ADCCONV).
PWM Output 6 (PWM6).
Output of PLA Element 18 (PLAO[18]).
F1 P2.6/IRQ7/PLAO[20] I/O Digital I/O Port 2.6 (P2.6).
External Interrupt 7 (IRQ7).
Output of PLA Element 20 (PLAO[20]).
G1 P2.7/IRQ8/PLAO[21] I/O Digital I/O Port 2.7 (P2.7).
External Interrupt 8 (IRQ8).
Output of PLA Element 21 (PLAO[21]).
G3 P3.0/PRTADDR0/PLAI[12] I/O Digital I/O Port 3.0 (P3.0).
MDIO Port Address Bit 0 (PRTADDR0). See the digital inputs parameter in Table 1
for details.
Input to PLA Element 12 (PLAI[12]).
G2 P3.1/PRTADDR1/PLAI[13] I/O Digital I/O Port 3.1 (P3.1).
MDIO Port Address Bit 1 (PRTADDR1). See the digital inputs parameter in Table 1
for details.
Input to PLA Element 13 (PLAI[13]).
D3 P3.2/PRTADDR2/PLAI[14] I/O Digital I/O Port 3.2 (P3.2).
MDIO Port Address Bit 2 (PRTADDR2). See the digital inputs parameter in Table 1
for details.
Input to PLA Element 14 (PLAI[14]).
B3 P3.3/PRTADDR3/PLAI[15] I/O Digital I/O Port 3.3 (P3.3).
MDIO Port Address Bit 3 (PRTADDR3). See the digital inputs parameter in Table 1
for details.
Input of PLA Element 15 (PLAI[15]).
C11 P3.4/PRTADDR4/PLAO[26] I/O Digital I/O Port 3.4 (P3.4).
MDIO Port Address Bit 4 (PRTADDR4). See the digital inputs parameter in Table 1
for details.
Output of PLA Element 26 (PLAO[26]).
H1 P3.5/MCK/PLAO[27] I/O Digital I/O Port 3.5 (P3.5).
MDIO Clock (MCK) See the digital inputs parameter in Table 1 for more details.
Output of PLA Element 27 (PLAO[27]).
H3 MDIO I/O MDIO Data.
E9 SWCLK I Serial Wire Debug Clock.
E10 SWDIO I/O Serial Wire Bidirectional Data.
F11 VREF_1V2 S 1.2 V Reference. This pin cannot be used to source current externally. Connect
VREF_1V2 to AGNDx via a 470 nF capacitor.
A11 IREF AI IDAC Reference Current. This pin generates the reference current for the IDACs
and is set by an external resistor, R
EXT
. Connect R
EXT
from IREF to AGND4.
J6 AIN0 AI Analog Input 0.
J7 AIN1 AI Analog Input 1.
J8 AIN2 AI Analog Input 2.
K8 AIN3 AI Analog Input 3.
L8 AIN4 AI Analog Input 4.
L9
AIN5
AI
Analog Input 5. AIN5 can be the negative input for the comparator.
K9 AIN6 AI Analog Input 6. AIN6 is also the positive input for the comparator.
J9 AIN7 AI Analog Input 7.
Rev. 0 | Page 20 of 26

EVAL-ADUCM320IQSPZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Development Boards & Kits - ARM ADUCM320i Quick Start Plus Dev. Kit
Lifecycle:
New from this manufacturer.
Delivery:
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