IDT
®
12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15
9ZX21201
12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
3
Pin Description
PIN # PIN NAME TYPE DESCRIPTION
1 VDDA PWR 3.3V power for the PLL core.
2 GNDA PWR Ground pin for the PLL core.
3 IREF OUT
This pin establishe s the referen ce for the differential current-mode output pairs. It requires a fixed precision
resistor to ground. 475ohm is the standard value for 100ohm differential impedance. Other impedances require
different values. See data sheet.
4 100M_133M # IN
3.3V Input to select operating frequency
See Functionality Table for Definition
5 H IBW_BYPM_LOBW# IN
Trilevel input to select High BW, Bypass or Low BW mode.
See PLL Operating Mode Table for Details.
6CKPWRGD_PD# IN
Notifies device to sample latched inputs and start up on first high assertion, or exit Power Down Mode on
subsequent assertions. Low enters Power Down Mode.
7 GND PWR Ground pin.
8 VDDR PWR
3.3V power for differential inpu t clock (receiver). This VDD should be treated as an analog power rail and
filtered a
ro
riatel
.
9 DIF_IN IN 0.7 V Differential TRUE in
ut
10 DIF_IN# IN 0.7 V Differential Com
lementar
In
ut
11 SMB_A0_tri IN
SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A1 to decode 1 of 9 SMBus
Addresses.
12 SMBDAT I/
Data
in of SMBUS circuitr
, 5V tolerant
13 SMBCLK IN Clock
in of SMBUS circuitr
, 5V tolerant
14 SMB_A1_tri IN
SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A0 to decode 1 of 9 SMBus
Addresses.
15 DFB_OUT# OUT
Complementary half of differential feedback output, provides feedback signal to the PLL for synchronization
with in
ut clock to e lim ina te
hase error.
16 DFB_OUT OUT
True half of differential feedback output, provides feedback signal to the PLL for synchronization with the input
clock t o elimi nate
hase error.
17 DIF_0 OUT 0.7V differential true clock output
18 DIF_0# OUT 0.7V differential Complementary clock output
19 vOE0# IN
Active low input for enabling DIF pair 0.
1 =disable out
uts, 0 = enable out
uts
20 vOE1# IN
Active low input for enabling DIF pair 1.
1 =disable out
uts, 0 = enable out
uts
21 DIF_1 OUT 0.7V differential true clock output
22 DIF_1# OUT 0.7V differential Complementary clock output
23 GND PWR Ground pin.
24 VDD PWR Power supply, nominal 3.3V
25 VDD PWR Power supply, nominal 3.3V
26 DIF_2 OUT 0.7V differential true clock output
27 DIF_2# OUT 0.7V differential Complementary clock output
28 vOE2# IN
Active low input for enabling DIF pair 2.
1 =disable outputs, 0 = enable outp uts
29 vOE3# IN
Active low input for enabling DIF pair 3.
1 =disable outputs, 0 = enable outp uts
30 DIF_3 OUT 0.7V differential true clock output
31 DIF_3# OUT 0.7V differential Complementary clock output
32 VDD PWR Power supply, nominal 3.3V
