IDT
®
12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15
9ZX21201
12-Output Differential Z-buffer for PCIe Gen2/3 and QPI
7
Electrical Characteristics - Skew and Differential Jitter Parameters
T
A
= T
COM
; Supply Voltage V
DD/
V
DDA
= 3.3 V +/-5%
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS NOTES
CLK_IN, DIF[x:0] t
SPO_PLL
Input-to-Output Skew in PLL mode
nominal value @ 25°C, 3.3V
-100 29 100 ps 1,2,4,5,8
CLK_IN, DIF[x:0] t
PD_BYP
Input-to-Output Skew in Bypass mode
nominal value @ 25°C, 3.3V
2.5 3.7 4.5 ns 1,2,3,5,8
CLK_IN, DIF[x:0] t
DSPO_PLL
Input-to-Output Skew Varation in PLL mode
across volta
e and temperature
-50 50 ps 1,2,3,5,8
CLK_IN, DIF[x:0] t
DSPO_BYP
Input-to-Output Skew Varation in Bypass mode
across voltage and temperature
-250 250 ps 1,2,3,5,8
CLK_IN, DIF[x:0] t
DTE
Random Differential Tracking error beween two
9ZX devices in Hi BW Mode
2.9 5
ps
(rms)
1,2,3,5,8
CLK_IN, DIF[x:0] t
DSSTE
Random Differential Spread Spectrum Tracking
error beween two 9ZX devices in Hi BW Mode
14 75 ps 1,2,3,5,8
DIF{x:0] t
SKEW_ALL
Output-to-Output Skew across all outputs
(Common to Bypass and PLL mode)
32 65 ps 1,2,3,8
PLL Jitter Peaking j
eak-hibw
LOBW#_BYPASS_HIBW = 1 0 1.8 2.5 dB 7,8
PLL Jitter Peaking j
eak-lobw
LOBW#_BYPASS_HIBW = 0 0 0.7 2 dB 7,8
PLL Bandwidth pll
HIBW
LOBW#_BYPASS_HIBW = 1 2 3.1 4 MHz 8,9
PLL Bandwidth pll
LOBW
LOBW#_BYPASS_HIBW = 0 0.7 1.1 1.4 MHz 8,9
Duty Cycle t
DC
Measured differentially, PLL Mode 45 49.6 55 % 1
Duty Cycle Distortion t
DCD
Measured differentially, Bypass Mode
@100MHz
-2 -0.2 2 % 1,10
PLL mode 15.7 50 ps 1,11
Additive Jitter in Bypass Mode 0.1 50 ps 1,11
Notes for preceding table:
6.
t is the period of the input clock
7
Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
8.
Guaranteed by desi
n and characterization, not 100% tested in production.
9
Measured at 3 db down or half power point.
10
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
11
Measured from differential waveform
3
All B
ass Mode In
ut-to-Out
ut s
ecs refer to the timin
between an in
ut ed
e and the s
ecific out
ut ed
e created b
it.
4
This
arameter is deterministic for a
iven device
5
Measured with sco
e avera
in
on to find mean value.
Jitter, Cycle to cycle t
jcyc-cyc
1
Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
2
Measured from differential cross-
oint to differential cross-
oint. This
arameter can be tuned with external feedback
ath
if
resent.
