9ZX21201AKLFT Datasheet 9ZX21201AKLFT, 9ZX21201AKLF, 9ZX21201BKLF | P10-P12

IDT

12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15

9ZX21201

12-Output Differential Z-buffer for PCIe Gen2/3 and QPI

General SMBus serial interface information for the 9ZX21201

How to Write:

• Controller (host) sends a start bit.

• Controller (host) sends the write address XX

(H)

• IDT clock will

acknowledge

• Controller (host) sends the beginning byte location = N

• IDT clock will

acknowledge

• Controller (host) sends the data byte count = X

• IDT clock will

acknowledge

• Controller (host) starts sending

Byte N through

Byte N + X -1

• IDT clock will

acknowledge

each byte

one at a time

• Controller (host) sends a Stop bit

How to Read:

• Controller (host) will send start bit.

• Controller (host) sends the write address XX

(H)

• IDT clock will

acknowledge

• Controller (host) sends the begining byte

location = N

• IDT clock will

acknowledge

• Controller (host) will send a separate start bit.

• Controller (host) sends the read addressYY

(H)

• IDT clock will

acknowledge

• IDT clock will send the data byte count = X

• IDT clock sends

Byte N + X -1

• IDT clock sends

Byte 0 through byte X (if X

(H)

was written to byte 8)

• Controller (host) will need to acknowledge each byte

• Controllor (host) will send a not acknowledge bit

• Controller (host) will send a stop bit

IDT (Slave/Receiver)

ACK

Byte N + X - 1

Data Byte Count = X

innin

Byte N

stoP bit

X Byte

Index Block Write Operation

Slave Address XX

(

)

Beginning Byte = N

WRite

starT bit

Controller (Host)

TstarT bit

WR WRite

RT Repeat starT

RD ReaD

Beginning Byte N

Byte N + X - 1

N Not acknowledge

PstoP bit

IDT

(

Slave/Receiver

)

Controller (Host)

X Byte

ACK

Data Byte Count = X

ACK

Slave Address YY

(

)

Index Block Read Operation

Slave Address XX

(

)

Beginning Byte = N

ACK

Note: XX

(H)

is defined by SMBus address select pins.

IDT

12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15

9ZX21201

12-Output Differential Z-buffer for PCIe Gen2/3 and QPI

SMBusTable: PLL Mode, and Frequency Select Register

Pin # Name Control Function T

e 0 1 Default

Bit 7

PLL Mode 1 PLL O

eratin

Mode Rd back 1

Latch

Bit 6

PLL Mode 0 PLL O

eratin

Mode Rd back 0

Latch

Bit 5

Bit 4

Bit 3 PLL_SW_EN Enable S/W control of PLL B

RW HW Latch S/W Control 0

Bit 2 PLL Mode 1 PLL O

eratin

Mode 1 RW 1

Bit 1 PLL Mode 0 PLL O

eratin

Mode 1 RW 1

Bit 0

100M_133M# Fre

uenc

Select Readback

133MHz 100MHz

Latch

SMBusTable: Output Control Register

Pin # Name Control Function T

e 0 1 Default

Bit 7

DIF_7_En Out

ut Control - '0' overrides OE#

in RW 1

Bit 6

DIF_6_En Out

ut Control - '0' overrides OE#

in RW 1

Bit 5

DIF_5_En Out

ut Control - '0' overrides OE#

in RW 1

Bit 4

DIF_4_En Out

ut Control - '0' overrides OE#

in RW 1

Bit 3

DIF_3_En Out

ut Control - '0' overrides OE#

in RW 1

Bit 2

DIF_2_En Out

ut Control - '0' overrides OE#

in RW 1

Bit 1

DIF_1_En Out

ut Control - '0' overrides OE#

in RW 1

Bit 0

DIF_0_En Out

ut Control - '0' overrides OE#

in RW 1

SMBusTable: Output Control Register

Pin # Name Control Function T

e 0 1 Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

DIF_11_En Out

ut Control - '0' overrides OE#

in RW 1

Bit 2

DIF_10_En Out

ut Control - '0' overrides OE#

in RW 1

Bit 1

DIF_9_En Out

ut Control - '0' overrides OE#

in RW 1

Bit 0

DIF_8_En Out

ut Control - '0' overrides OE#

in RW 1

SMBusTable: Reserved Register

Pin # Name Control Function T

e 0 1 Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

See PLL Operating Mode

Readback Table

See PLL Operating Mode

Readback Table

Low/Low Enable

30/31

te 3

50/51

59/60

54/55

te 2

te 0

These bits

available in B

rev onl

te 1

47/46

64/63

26/27

21/22

17/18

43/42

39/38

35/34

Low/Low Enable

Reserved

IDT

12-Output Differential Z-buffer for PCIe Gen2/3 and QPI 1682D- 11/19/15

9ZX21201

12-Output Differential Z-buffer for PCIe Gen2/3 and QPI

SMBusTable: Reserved Register

Pin # Name Control Function T

e 0 1 Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBusTable: Vendor & Revision ID Register

Pin # Name Control Function T

e 0 1 Default

Bit 7

RID3 R X

Bit 6

RID2 R X

Bit 5

RID1 R X

Bit 4

RID0 R X

Bit 3

VID3 R 0

Bit 2

VID2 R 0

Bit 1

VID1 R 0

Bit 0

VID0 R 1

SMBusTable: DEVICE ID

Pin # Name Control Function T

e 0 1 Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

SMBusTable: Byte Count Register

Pin # Name Control Function T

e 0 1 Default

Bit 7

Bit 6

Bit 5

Bit 4

BC4 RW 0

Bit 3

BC3 RW 1

Bit 2

BC2 RW 0

Bit 1

BC1 RW 0

Bit 0

BC0 RW 0

SMBusTable: Reserved Register

Pin # Name Control Function T

e 0 1 Default

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

Device ID 5

Device ID 6

Device ID 0

Default value is 8 hex, so 9

bytes (0 to 8) will be read back

by default.

Reserved

1201 is 201 decimal or C9 hex

Device ID 7

(

MSB

)

te 7

te 5

te 6

te 4

Reserved

te 8

Device ID 2

Device ID 1

Device ID 4

REVISION ID

A rev = 0000

B rev = 0001

Reserved

VENDOR ID

Device ID 3

0001 for IDT/ICS

Writing to this register configures how

many bytes will be read back.

Reserved

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P16

9ZX21201AKLFT

Mfr. #:

Buy 9ZX21201AKLFT

Manufacturer:

IDT

Description:

Clock Buffer HIGH PERF. ZDB

Lifecycle:

New from this manufacturer.

Delivery:

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9ZX21201AKLFT

9ZX21201AKLFT

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