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HCPL-090J-500E

P1-P3P4-P6P7-P9P10-P12P13-P14
10
5V operation: Electrical Specications
Test conditions that are not specied can be anywhere within the recommended operating range.
All typical specications are at T
A
=+25°C, V
DD1
= V
DD2
= +5.0V.
Parameter Symbol Min. Typ. Max. Units Test Conditions
Quiescent Supply Current 1 I
DD1
mA V
IN
= 0V
HCPL-9000/-0900 0.012 0.018
HCPL-9030/-0930 0.012 0.018
HCPL-9031/-0931 2.5 3.0
HCPL-900J/-090J 0.024 0.036
HCPL-901J/-091J 5.0 6.0
HCPL-902J/-092J 2.5 3.0
Quiescent Supply Current 2 I
DD2
mA V
IN
= 0V
HCPL-9000/-0900 5.0 6.0
HCPL-9030/-0930 5.0 6.0
HCPL-9031/-0931 2.5 3.0
HCPL-900J/-090J 8.0 12.0
HCPL-901J/-091J 5.0 6.0
HCPL-902J/-092J 6.0 9.0
Logic Input Current I
IN
-10 10 µA
Logic High Output Voltage V
OH
V
DD2
– 0.1 V
DD2
V I
OUT
= -20 µA, V
IN
=V
IH
0.8*V
DD2
V
DD2
– 0.5 V I
OUT
= -4 mA, V
IN
=V
IH
Logic Low Output Voltage V
OL
0 0.1 V I
OUT
= 20 µA, V
IN
=V
IL
0.5 0.8 V I
OUT
= 4 mA, V
IN
=V
IL
Switching Specications
Maximum Data Rate 100 110 MBd C
L
= 15 pF
Clock Frequency fmax 50 MHz
Propagation Delay Time to Logic t
PHL
10 15 ns
Low Output
Propagation Delay Time to Logic t
PLH
10 15 ns
High Output
Pulse Width t
PW
10 ns
Pulse Width Distortion
[1]
|PWD| 2 3 ns
|t
PHL
– t
PLH
|
Propagation Delay Skew
[2]
t
PSK
4 6 ns
Output Rise Time (10 – 90%) t
R
1 3 ns
Output Fall Time (10 – 90%) t
F
1 3 ns
Propagation Delay Enable to Output (Single Channel)
High to High Impedance t
PHZ
3 5 ns
Low to High Impedance t
PLZ
3 5 ns
High Impedance to High t
PZH
3 5 ns
High Impedance to Low t
PZL
3 5 ns
Channel-to-Channel Skew t
CSK
2 3 ns
(Dual and Quad Channels)
Common Mode Transient Immunity |CM
H
| 15 18 kV/µs V
cm
= 1000V
(Output Logic High or Logic Low)
[3]
|CM
L
|
Notes:
1. PWD is dened as |t
PHL
-t
PLH
|. %PWD is equal to the PWD divided by the pulse width.
2. t
PSK
is equal to the magnitude of the worst case dierence in t
PHL
and/or t
PLH
that will be seen between units at 25°C.
3. CM
H
is the maximum common mode voltage slew rate that can be sustained while maintaining V
OUT
> 0.8V
DD2
. CM
L
is the maximum common mode
input voltage that can be sustained while maintaining V
OUT
< 0.8V. The common mode voltage slew rates apply to both rising and falling common mode
voltage edges.
This product has been tested for electrostatic sensitivity to the limits stated in the specications. However, Avago recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.
11
Mixed 5V/3.3V or 3.3V/5V operation: Electrical Specications
Test conditions that are not specied can be anywhere within the recommended operating range.
All typical specications are at T
A
=+25°C, V
DD1
= +5.0V, V
DD2
= +3.3V.
Parameter Symbol Min. Typ. Max. Units Test Conditions
HCPL-9000/-0900 I
DD1
0.012 0.018
HCPL-9030/-0930 0.012 0.018
HCPL-9031/-0931 2.5 3.0
HCPL-900J/-090J 0.024 0.036
HCPL-901J/-091J 5.0 6.0
HCPL-902J/-092J 2.5 3.0
Quiescent Supply Current 2 I
DD2
mA V
IN
= 0V
HCPL-9000/-0900 5.0 6.0
HCPL-9030/-0930 5.0 6.0
HCPL-9031/-0931 2.5 3.0
HCPL-900J/-090J 8.0 12.0
HCPL-901J/-091J 5.0 6.0
HCPL-902J/-092J 6.0 9.0
Logic Input Current I
IN
-10 10 µA
Logic High Output Voltage V
OH
V
DD2
– 0.1 V
DD2
V I
OUT
= -20 µA, V
IN
=V
IH
0.8*V
DD2
V
DD2
– 0.5 V I
OUT
= -4 mA, V
IN
=V
IH
Logic Low Output Voltage V
OL
0 0.1 V I
OUT
= 20 µA, V
IN
=V
IL
0.5 0.8 V I
OUT
= 4 mA, V
IN
=V
IL
Switching Specications
Maximum Data Rate 100 110 MBd C
L
= 15 pF
Clock Frequency fmax 50 MHz
Propagation Delay Time to Logic t
PHL
12 18 ns
Low Output
Propagation Delay Time to Logic t
PLH
12 18 ns
High Output
Pulse Width t
PW
10 ns
Pulse Width Distortion
[1]
|PWD| 2 3 ns
|t
PHL
– t
PLH
|
Propagation Delay Skew
[2]
t
PSK
4 6 ns
Output Rise Time (10 – 90%) t
R
2 4 ns
Output Fall Time (10 – 90%) t
F
2 4 ns
Propagation Delay Enable to Output (Single Channel)
High to High Impedance t
PHZ
3 5 ns
Low to High Impedance t
PLZ
3 5 ns
High Impedance to High t
PZH
3 5 ns
High Impedance to Low t
PZL
3 5 ns
Channel-to-Channel Skew t
CSK
2 3 ns
(Dual and Quad Channels)
Common Mode Transient Immunity |CM
H
| 15 18 kV/µs V
cm
= 1000V
(Output Logic High or Logic Low)
[3]
|CM
L
|
Notes:
1. PWD is dened as |t
PHL
-t
PLH
|. %PWD is equal to the PWD divided by the pulse width.
2. t
PSK
is equal to the magnitude of the worst case dierence in t
PHL
and/or t
PLH
that will be seen between units at 25°C.
3. CM
H
is the maximum common mode voltage slew rate that can be sustained while maintaining V
OUT
> 0.8V
DD2
. CM
L
is the maximum common mode
input voltage that can be sustained while maintaining V
OUT
< 0.8V. The common mode voltage slew rates apply to both rising and falling common mode
voltage edges.
This product has been tested for electrostatic sensitivity to the limits stated in the specications. However, Avago recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.
12
Applications Information
Power Consumption
The HCPL-90xx and HCPL-09xx CMOS digital isolators
achieves low power consumption from the manner by
which they transmit data across isolation barrier. By
detecting the edge transitions of the input logic signal
and converting this to a narrow current pulse, which
drives the isolation barrier, the isolator then latches the
input logic state in the output latch. Since the current
pulses are narrow, about 2.5 ns wide, the power consump-
tion is independent of mark-to-space ratio and solely
dependent on frequency.
The approximate power supply current per channel is:
I(Input) = 40(f/fmax)(1/4) mA
where f = operating frequency, fmax = 50 MHz.
Signal Status on Start-up and Shut Down
To minimize power dissipation, the input signals to the
channels of HCPL-90xx and HCPL-09xx digital isolators
are dierentiated and then latched on the output side of
the isolation barrier to reconstruct the signal. This could
result in an ambiguous output state depending on power
up, shutdown and power loss sequencing. Therefore, the
designer should consider the inclusion of an initializa-
tion signal in this start-up circuit. Initialization consists of
toggling the input either high then low or low then high.
Figure 1. Functional Diagram of Single Channel HCPL-0900 or HCPL-0900.
1
2
3
45
6
7
8
V
DD1
IN
1
C1
C2
Note: C1, C2 = 47 nF ceramic capacitors
NC
GND
1
V
DD2
OUT
1
GND
2
HCPL-9000
or
HCPL-0900
V
OE
Figure 2. Recommended Printed Circuit Board Layout.
C2
V
DD2
OUT
1
GND
2
V
DD1
GND
1
IN
1
C1
V
OE
HCPL-9000
or
HCPL-0900
Bypassing and PC Board Layout
The HCPL-90xx and HCPL-09xx digital isolators are
extremely easy to use. No external interface circuitry is
required because the isolators use high-speed CMOS IC
technology allowing CMOS logic to be connected directly
to the inputs and outputs. As shown in Figure 1, the only
external components required for proper operation are
two 47 nF ceramic capacitors for decoupling the power
supplies. For each capacitor, the total lead length between
both ends of the capacitor and the power-supply pins
should not exceed 20 mm. Figure 2 illustrates the recom-
mended printed circuit board layout for the HCPL-9000
or HCPL-0900. For data rates in excess of 10MBd, use of
ground planes for both GND
1
and GND
2
is highly recom-
mended.
P1-P3P4-P6P7-P9P10-P12P13-P14

HCPL-090J-500E

Mfr. #:
Buy HCPL-090J-500E
Manufacturer:
Broadcom / Avago
Description:
Digital Isolators Digital Isolator 100MBd
Lifecycle:
New from this manufacturer.
Delivery:
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