9
3.3V operation: Electrical Specications
Test conditions that are not specied can be anywhere within the recommended operating range.
All typical specications are at T
A
=+25°C, V
DD1
= V
DD2
= +3.3V.
Parameter Symbol Min. Typ. Max. Units Test Conditions
Quiescent Supply Current 1 I
DD1
mA V
IN
= 0V
HCPL-9000/-0900 0.008 0.01
HCPL-9030/-0930 0.008 0.01
HCPL-9031/-0931 1.5 2.0
HCPL-900J/-090J 0.018 0.02
HCPL-901J/-091J 3.3 4.0
HCPL-902J/-092J 1.5 2.0
Quiescent Supply Current 2 I
DD2
mA V
IN
= 0V
HCPL-9000/-0900 3.3 4.0
HCPL-9030/-0930 3.3 4.0
HCPL-9031/-0931 1.5 2.0
HCPL-900J/-090J 5.5 8.0
HCPL-901J/-091J 3.3 4.0
HCPL-902J/-092J 3.0 6.0
Logic Input Current I
IN
-10 10 µA
Logic High Output Voltage V
OH
V
DD2
–0.1 V
DD2
V I
OUT
= -20 µA, V
IN
=V
IH
0.8*V
DD2
V
DD2
–0.5 V I
OUT
= -4 mA, V
IN
=V
IH
Logic Low Output Voltage V
OL
0 0.1 V I
OUT
= 20 µA, V
IN
=V
IL
0.5 0.8 V I
OUT
= 4 mA, V
IN
=V
IL
Switching Specications
Maximum Data Rate 100 110 MBd C
L
= 15 pF
Clock Frequency fmax 50 MHz
Propagation Delay Time to Logic t
PHL
12 18 ns
Low Output
Propagation Delay Time toLogic t
PLH
12 18 ns
High Output
Pulse Width t
PW
10 ns
Pulse Width Distortion
[1]
|PWD| 2 3 ns
|t
PHL
– t
PLH
|
Propagation Delay Skew
[2]
t
PSK
4 6 ns
Output Rise Time (10 – 90%) t
R
2 4 ns
Output Fall Time (10 – 90%) t
F
2 4 ns
Propagation Delay Enable to Output (Single Channel)
High to High Impedance t
PHZ
3 5 ns
Low to High Impedance t
PLZ
3 5 ns
High Impedance to High t
PZH
3 5 ns
High Impedance to Low t
PZL
3 5 ns
Channel-to-Channel Skew t
CSK
2 3 ns
(Dual and Quad Channels)
Common Mode Transient Immunity |CM
H
| 15 18 kV/µs V
cm
= 1000V
(Output Logic High or Logic Low)
[3]
|CM
L
|
Notes:
1. PWD is dened as |t
PHL
-t
PLH
|. %PWD is equal to the PWD divided by the pulse width.
2. t
PSK
is equal to the magnitude of the worst case dierence in t
PHL
and/or t
PLH
that will be seen between units at 25°C.
3. CM
H
is the maximum common mode voltage slew rate that can be sustained while maintaining V
OUT
> 0.8V
DD2
. CM
L
is the maximum common mode
input voltage that can be sustained while maintaining V
OUT
< 0.8V. The common mode voltage slew rates apply to both rising and falling common mode
voltage edges.
This product has been tested for electrostatic sensitivity to the limits stated in the specications. However, Avago recommends that all integrated circuits
be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to
complete failure.
