13
Propagation Delay, Pulse Width Distortion and Propaga-
tion Delay Skew
Propagation Delay is a gure of merit, which describes
how quickly a logic signal propagates through a system
as illustrated in Figure 3.
Figure 3. Timing Diagrams to Illustrate Propagation Delay, t
PLH
and t
PHL
.
Figure 4. Timing Diagrams to Illustrate Propagation Delay Skew.
V
IN
V
OUT
V
OUT
V
IN
t
PSK
50%
50%
2.5 V
CMOS
2.5 V
CMOS
Figure 5. Parallel Data Transmission.
DATA
DATA
INPUTS
CLOCK
OUTPUTS
CLOCK
t
PSK
t
PSK
INPUT
OUTPUT
5 V CMOS
2.5 V CMOS
0 V
V
OH
V
OL
V
OUT
V
IN
t
PLH
t
PHL
50%
10%
90%
90%
10%
The propagation delay from low to high, t
PLH
, is the
amount of time required for an input signal to propagate
to the output, causing the output to change from low to
high. Similarly, the propagation delay from high to low,
t
PHL
, is the amount of time required for the input signal to
propagate to the output, causing the output to change
from high to low.
Pulse Width Distortion, PWD, is the dierence between t
PHL
and t
PLH
and often determines the maximum data rate ca-
pability of a transmission system. PWD can be expressed in
percent by dividing the PWD (in ns) by the minimum pulse
width (in ns) being transmitted. Typically, PWD on the order
of 20– 30% of the minimum pulse width is tolerable.
Propagation Delay Skew, t
PSK
, and Channel-to-Channel
Skew, t
CSK
, are critical parameters to consider in parallel
data transmission applications where synchronization of
signals on parallel data lines is a concern. If the parallel
data is being sent through channels of the digital
isolators, differences in propagation delays will cause
the data to arrive at the outputs of the digital isolators
at dierent times. If this dierence in propagation delay
is large enough, it will limit the maximum transmission
rate at which parallel data can be sent through the digital
isolators.
t
PSK
is dened as the dierence between the minimum and
maximum propagation delays, either t
PLH
or t
PHL
, among two
or more devices which are operating under the same con-
ditions (i.e., the same drive current, supply voltage, output
load, and operating temperature). t
CSK
is dened as the
dierence between the minimum and maximum propaga-
tion delays, either t
PLH
or t
PHL
, among two or more channels
within a single device (applicable to dual and quad channel
devices) which are operating under the same conditions.
As illustrated in Figure 4, if the inputs of two or more
devices are switched either ON or OFF at the same time,
t
PSK
is the dierence between the minimum propagation
delay, either t
PLH
or t
PHL
, and the maximum propagation
delay, either t
PLH
or t
PHL
.
As mentioned earlier, t
PSK
, can determine the maximum
parallel data transmission rate. Figure 5 shows the timing
diagram of a typical parallel data transmission application
with both the clock and data lines being sent through the
digital isolators. The gure shows data and clock signals at
the inputs and outputs of the digital isolators. In this case,
the data is clocked o the rising edge of the clock.
