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8735AY-31LF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
1©2016 Integrated Device Technology, Inc Revision B January 27, 2016
General Description
The 8735-31 is a highly versatile 1:5 Differential -to-3.3V LVPECL
Clock Generator. The 8735-31 has a fully integrated PLL and can
be configured as zero delay buffer, multiplier or divider, and has an
output frequency range of 15.625MHz to 350MHz. The reference
divider, feedback divider and output divider are each
programmable, thereby allowing for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external
feedback allows the device to achieve “zero delay” between the
input clock and the output clocks. The PLL_SEL pin can be used
to bypass the PLL for system test and debug purposes. In bypass
mode, the reference clock is routed around the PLL and into the
internal output dividers.
Features
• Five differential 3.3V LVPECL output pairs
• Selectable differential clock inputs
• CLKx/nCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
• Output frequency range: 15.625MHz to 350MHz
• Input frequency range: 15.625MHz to 350MHz
• VCO range: 250MHz to 700MHz
• External feedback for “zero delay” clock regeneration
with configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Cycle-to-cycle jitter: 60ps (maximum)
• Output skew: 35ps (maximum)
• Static phase offset: 55ps ± 125ps
• Full 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
SEL0
SEL1
CLK0
nCLK0
CLK1
nCLK1
CLK_SEL
MR
V
CCO
Q3
nQ3
Q2
nQ2
Q1
nQ1
V
CCO
VCC
nFB_IN
FB_IN
SEL2
V
EE
nQ0
Q0
V
CCO
PLL_SE
L
VCCA
SEL3
V
EE
Q4
nQ4
V
CCO
VCC
Block Diagram
PLL_SEL
FB_IN
nFB_IN
SEL0
SEL1
SEL2
SEL3
MR
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
÷2, ÷4, ÷8,
÷16,
÷32
, ÷64, ÷128
Pullup
Pullup
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
0
1
CLK0
nCLK0
Pulldown
Pullup
CLK1
nCLK1
Pulldown
Pullup
CLK_SEL
Pulldown
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Pin Assignment
8735-31
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
8735-31
Data Sheet
1:5, Differential-to-3.3V LVPECL Zero
Delay Clock Generator
2©2016 Integrated Device Technology, Inc Revision B January 27, 2016
8735-31 Data Sheet
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 2,
12, 29
SEL0, SEL1,
SEL2, SEL3
Input Pulldown
Determines output divider values in Table 3.
LVCMOS / LVTTL interface levels.
3 CLK0 Input Pulldown Non-inverting differential clock input.
4 nCLK0 Input Pullup Inverting differential clock input.
5 CLK1 Input Pulldown Non-inverting differential clock input.
6 nCLK1 Input Pullup Inverting differential clock input.
7 CLK_SEL Input Pulldown
Clock select input. When HIGH, selects CLK1/nCLK1. When LOW, selects
CLK0/nCLK0. LVCMOS / LVTTL interface levels.
8 MR Input Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
9, 32 V
CC
Power Core supply pins.
10 nFB_IN Input Pullup
Inverting differential feedback input to phase detector for regenerating clocks
with “zero delay.”
11 FB_IN Input Pulldown
Non-inverted differential feedback input to phase detector for regenerating
clocks with
“zero delay.”
13, 28 V
EE
Power Negative supply pins.
14, 15 nQ0, Q0 Output Differential output pair. LVPECL interface levels.
16, 17, 24, 25 V
CCO
Power Output supply pins.
18, 19 nQ1, Q1 Output Differential output pair. LVPECL interface levels.
20, 21 nQ2, Q2 Output Differential output pair. LVPECL interface levels..
22, 23 nQ3, Q3 Output Differential output pair. LVPECL interface levels.
26, 27 nQ4, Q4 Output Differential output pair. LVPECL interface levels.
30 V
CCA
Power Analog supply pin.
31 PLL_SEL Input Pullup
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS/LVTTL interface levels.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
3©2016 Integrated Device Technology, Inc Revision B January 27, 2016
8735-31 Data Sheet
Function Tables
Table 3A. Control Input Function Table
Inputs Outputs
PLL_SEL = 1
PLL Enable Mode
SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz) Q0:Q4, nQ0:nQ4
0000 125 - 350 ÷1
0001 62.5 - 175 ÷1
0010 31.25 - 87.5 ÷1
0011 15.625 - 43.75 ÷1
0100 125 - 350 ÷2
0101 62.5 - 175 ÷2
0110 31.25 - 87.5 ÷2
0111 125 - 350 ÷4
1000 62.5 - 175 ÷4
1001 125 - 350 ÷8
1010 62.5 - 175 x2
1011 31.25 - 87.5 x2
1100 15.625 - 43.75 x2
1101 31.25 - 87.5 x4
1110 15.625 - 43.75 x4
1111 15.625 - 43.75 x8
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

8735AY-31LF

Mfr. #:
Buy 8735AY-31LF
Manufacturer:
IDT
Description:
Clock Generators & Support Products 5 LVPECL OUT DIVIDER
Lifecycle:
New from this manufacturer.
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