OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

8735AY-31LF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
10©2016 Integrated Device Technology, Inc Revision B January 27, 2016
8735-31 Data Sheet
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perform- ance,
power supply isolation is required. The 8735-31 provides separate
power supplies to isolate any high switching noise from the outputs
to the internal PLL. V
CC,
V
CCA
and V
CCO
should be individually
connected to the power supply plane through vias, and 0.01µF
bypass capacitors should be used for each pin. Figure 1 illustrates
this for a generic V
CC
pin and also shows that V
CCA
requires that an
additional 10 resistor along with a 10F bypass capacitor be
connected to the V
CCA
pin. The 10 resistor can also be replaced by
a ferrite bead.
Figure 1. Power Supply Filtering
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
CC
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock swing
is only 2.5V and V
CC
= 3.3V, V_REF should be 1.25V and R2/R1 =
0.609.
Figure 2. Single-Ended Signal Driving Differential Input
V
CC
V
CCA
3.3V
10µF0.01µF
0.01µF
V_REF
Single Ended Clock Input
V
CC
CLKx
nCLKx
R1
1K
C1
0.1u R2
1K
11©2016 Integrated Device Technology, Inc Revision B January 27, 2016
8735-31 Data Sheet
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V
SWING
and V
OH
must meet the
V
PP
and V
CMR
input requirements. Figures 3A to 3F show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example, in Figure 3A, the input termination applies for IDT
HiPerClockS open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
Figure 3A. HiPerClockS CLK/nCLK Input
Driven by an IDT Open Emitter
HiPerClockS LVHSTL Driver
Figure 3C. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 3E. HiPerClockS CLK/nCLK Input
Driven by a 3.3V HCSL Driver
Figure 3B. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVPECL Driver
Figure 3D. HiPerClockS CLK/nCLK Input
Driven by a 3.3V LVDS Driver
Figure 3F. HiPerClockS CLK/nCLK Input
Driven by a 2.5V SSTL Driver
R1
50Ω
R2
50Ω
1.8V
Zo = 50Ω
Zo = 50Ω
CLK
nCLK
3.3V
LVHSTL
IDT
LVHSTL Driver
Differential
Input
H
CSL
*R
3
*
R4
C
L
K
n
C
L
K
3
.
3V
3
.
3V
Diff
e
r
e
nti
a
l
In
p
u
t
CLK
nCLK
Differential
Input
SSTL
2.5V
Zo = 60
Ω
Zo = 60
Ω
2.5V
3.3V
R1
120
Ω
R2
120
Ω
R3
120
Ω
R4
120
Ω
12©2016 Integrated Device Technology, Inc Revision B January 27, 2016
8735-31 Data Sheet
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 4A and 4B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts
may exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
Figure 4A. 3.3V LVPECL Output Termination Figure 4B. 3.3V LVPECL Output Termination
R1
84
R2
84
3.3V
R3
125
R4
125
Z
o
= 50
Z
o
= 50
Input
3.3V
3.3V
+
_
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

8735AY-31LF

Mfr. #:
Buy 8735AY-31LF
Manufacturer:
IDT
Description:
Clock Generators & Support Products 5 LVPECL OUT DIVIDER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet