7©2016 Integrated Device Technology, Inc Revision B January 27, 2016
8735-31 Data Sheet
AC Electrical Characteristics
Table 6. AC Characteristics, V
CC
= V
CCA
= V
CCO
= 3.3V ± 5%, V
EE
= 0V, T
A
= 0°C to 70°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions,
when the PLL is locked and the input reference frequency is stable.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
f
MAX
Output Frequency 350 MHz
t
PD
Propagation Delay; NOTE 1 PLL_SEL = 0, f 350MHz 3.8 5.1 ns
tsk(o) Output Skew; NOTE 2, 3 35 ps
tsk(Ø) Static Phase Offset; NOTE 3, 4 PLL_SEL = 1 -70 55 +180 ps
tjit(cc) Cycle-to-Cycle Jitter; NOTE 3 60 ps
t
L
PLL Lock Time 1ms
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 200 750 ps
odc Output Duty Cycle 47 53 %
8©2016 Integrated Device Technology, Inc Revision B January 27, 2016
8735-31 Data Sheet
Parameter Measurement Information
3.3V Output Load AC Test Circuit
Phase Jitter and Static Phase Offset
Cycle-to-Cycle Jitter
Differential Input Level
Output Skew
Output Rise/Fall Time
SCOPE
Qx
nQx
V
EE
2V
1.3V± 0.165V
V
CC,
V
CCA,
V
CCO
nCLK0,
CLK0,
nFB_IN
FB_IN
t(Ø)
V
OH
V
OL
V
OH
V
OL
nCLK1
CLK1
tcycle n tcycle n+1
tjit(cc) =
|
tcycle n – tcycle n+1
|
1000 Cycles
nQ[0:4]
Q[0:4]
V
CC
V
EE
V
CMR
Cross Points
V
PP
nCLK0,
nCLK1
CLK0,
CLK1
nQx
Qx
nQy
Qy
nQ[0:4]
Q[0:4]
9©2016 Integrated Device Technology, Inc Revision B January 27, 2016
8735-31 Data Sheet
Parameter Measurement Information, continued
Output Duty Cycle/Pulse Width/Period Propagation Delay
Application Information
Recommendations for Unused Input and Output Pins
Inputs:
LVCMOS Control Pins
All control pins have internal pullups or pulldowns; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to ground.
FB_IN/nFB_IN Inputs
For applications not requiring the use of the differential input, both
FB_IN and nFB_IN can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from FB_IN to
ground.
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend that
there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
nQ[0:4]
Q[0:4]
t
PD

8735AY-31LF

Mfr. #:
Manufacturer:
IDT
Description:
Clock Generators & Support Products 5 LVPECL OUT DIVIDER
Lifecycle:
New from this manufacturer.
Delivery:
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