TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 17 of 46
NXP Semiconductors
TEA19161T
Digital controller for high-efficiency resonant power supply
When the system is off, GATELS is on and GATEHS is off. The external bootstrap buffer
capacitor (C
SUPHS
) is charged via the SUPREG pin and an external diode. The system
remains in this state for at least the minimum on-time (t
on(min)
) of GATELS. Before entering
the next state, one of the following conditions must be fulfilled:
• The V
SNSCAP
voltage drops to below the minimum V
SNSCAP
voltage (V
ls(SNSCAP)
)
• The measured current exceeds the OCP level (see Section 7.6.6)
• The system is close to capacitive mode (see Section 7.6.5)
• The maximum on-time (t
on(max)
), a protection that maximizes the time the high-side or
low-side MOSFET is kept on, is exceeded.
In the next state, to avoid false detection of the HB peak voltage, the system waits until the
minimum non-overlap time (t
no(min)
) is exceeded. When it is exceeded, the system starts
to detect the end (= peak voltage) of the HB node. When it detects the peak of the HB
node and the measured resonant current is negative (or zero), it enters the next state.
If the system does not detect a peak at the HB node, it also enters the next state when the
maximum non-overlap time (t
no(max)
) is exceeded under the condition of a negative (or
zero) resonant current.
Finally, the third and fourth states (see Figure 11
) describe the GATEHS and GATEHS to
GATELS transition criteria which are the inverse of the first two states.
7.4.2 Low-power mode
At low loads, the operating frequency of a resonant converter increases. As a result, the
magnetization and switching losses increase. For this reason, the efficiency of a resonant
converter drops at low loads. A newly introduced low-power mode ensures high efficiency
at lower loads as well.
When the output power drops to below the P
t(lp)
level, the system enters the low-power
mode (see Figure 10
and Figure 12). It continues switching for 3 half-cycles (low-side,
high-side, low-side) with a fixed duty cycle of 67 %. To ensure a constant output power
level, it increases the energy per cycle (V
hs(SNSCAP)
V
ls(SNSCAP)
) at the same time. So
1/3 of the time the converter is in a "hold" period. The result is a 33 % magnetization and
switching losses reduction.
