TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 25 of 46
NXP Semiconductors
TEA19161T
Digital controller for high-efficiency resonant power supply
7.6.8 Overpower protection
The external capacitive/resistive divider connected to the SNSCAP pin must be chosen
such that:
The voltage difference between V
hs(SNSCAP)
and V
ls(SNSCAP)
equals V
opp(SNSCAP)
The voltage difference between V
hs(SNSCAP)
and V
ls(SNSCAP)
occurs at 125 % of the
maximum output power or at 175 %, depending on the settings
When the V
SNSCAP
(V
hs(SNSCAP)
V
ls(SNSCAP)
) exceeds the V
opp(SNSCAP)
voltage
difference, an internal counter is started. When this counter exceeds t
d(opp)
(50 ms/200 ms), the system enters a latched/safe restart protection as defined by the
external settings.
The voltage difference between V
hs(SNSCAP)
and V
ls(SNSCAP)
is also limited to
V
th(max)SNSCAP
, which then corresponds to an output power of 150 % or 200 %,
depending on the settings (see Figure 19
). If the output of the LLC converter requires
additional power, the output voltage drops as the power delivered by the LLC converter is
limited to 150 % or 200 %.
An additional option is to disable the overpower counter, using the external settings. In this
way, the overpower rating can be used as an extension of the typical power level.
Fig 19. TEA19161T overpower
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TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 26 of 46
NXP Semiconductors
TEA19161T
Digital controller for high-efficiency resonant power supply
7.7 External settings
Before the system starts switching, it reads the external settings. Using specific resistor
values at the GATELS, SNSSET, and SNSOUT pins, several internal settings can be
defined.
7.7.1 Burst period
Figure 20 shows how the internal regulated burst frequency can be set using the external
resistor connected to the SNSOUT pin.
The absolute value of the resistor connected between the SNSOUT pin and ground
(R
SNSOUT1
) defines the burst frequency. An accurate resistor of 1 % according to Table 4
is required. The OVP level can be set using resistor R
SNSOUT2
.
A low burst frequency is best for minimum audible noise. However, a high burst frequency
minimizes the output voltage ripple.
7.7.2 General settings
Variables on the OPP function can be set using resistor R
SNSSET1
connected to the
SNSSET pin (see Figure 21
).
Fig 20. External setting of the burst frequency
Table 4. External setting of the burst frequency
R
SNSOUT1
Burst frequency
22 k 200 Hz
15 k 400 Hz
10 k 800 Hz
6.8 k 1600 Hz
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Fig 21. External setting of the SNSSET pin
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TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 27 of 46
NXP Semiconductors
TEA19161T
Digital controller for high-efficiency resonant power supply
When the measured value of R
SNSSET1
<10k, the system assumes a shorted pin to
ground and the start-up is inhibited. At a value of 46.4 K, the system can of continuously
delivering the maximum power of 200 %.
The output power level at which the overpower timer is started can be set to 125 % or
175 %. Two corresponding timer values can be selected, 50 ms or 200 ms. Finally, the
value of R
SNSSET1
(see Table 5) can set the behavior of the overpower function (either a
1 s restart or latched). During this protection period, the SUPIC is regulated at its
V
start(SUPIC)
level.
7.7.3 Low-power mode/burst mode transition levels
To ensure the best efficiency, the system must enter the low-power mode and the burst
mode at high power levels. However, to ensure the best output ripple, these modes must
be entered at low-power levels. To choose the optimum level for a specific application, the
power transition levels at which the system enters the low-power mode and the burst
mode can be set externally.
Resistor R
SNSSET2
defines the power levels at which the system enters the low-power
mode and the burst mode. Table 6
gives an overview.
Table 5. General settings
R
SNSSET1
(k) Power capability
level (%)
OPP timer level
(%)
End of power
good timer (ms)
OPP timer (ms) Protection
< 10 no start-up
46.4 200 infinite
53.6 200 175 190 200 1 s restart
61.9 200 175 45 50 1 s restart
71.5 150 125 190 200 1 s restart
82.5 150 125 45 50 1 s restart
95.3 200 175 190 200 latched
110 200 175 45 50 latched
127 150 125 190 200 latched
147 150 125 45 50 latched

TEA19161T/2Y

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
Switching Controllers TEA19161T/SO16//2/REEL 13 Q1 DP
Lifecycle:
New from this manufacturer.
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