TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 28 of 46
NXP Semiconductors
TEA19161T
Digital controller for high-efficiency resonant power supply
[1] The values in this table are including the additional shift due to the internal (t
PD(SNSCAP)
) delay and a typical
external delay of 150 ns and 300 ns, respectively. When an external R + C network compensates these
delays, the levels in Table 6
can be lowered.
The power level at which the system enters the burst mode also depends on the defined
burst period. In this way, the optimum between efficiency and output voltage ripple can be
chosen.
7.8 Power good function
The TEA19161T provides a power good function via the SNSSET pin. At initialization, the
TEA19161T measures the resistors connected to the SNSSET pin to set internal
variables. After that, the pin is used for the power good function.
After the system has read the external settings (see Figure 5), the SNSSET output is
active high, enabling an external MOSFET. A secondary power good signal can be pulled
low using an external optocoupler.
When the system enters the operating state (see Figure 5
), the SNSSET output is pulled
low and the external power good signal becomes active high. Any required delay can be
achieved via an external R/C network.
Table 6. External setting of the high-power/low-power and low-power/burst transition
levels
R
SNSSET2
(k)
High-power => low-power
(%)
[1]
Burst mode
[1]
200 Hz (%) 400 Hz (%) 800 Hz (%) 1600 Hz (%)
125 9 9 9 9
6.8 25 12 12 12 12
15 37.5 9 9 9 10
27 37.5 12 12 12 13
47 50 9 10 11 12
82 50 12 13 15 17
180 62.5 9 10 12 14
open 62.5 12 15 17.5 20
a. Primary side b. Secondary side
Fig 22. Power good function
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