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TEA19161T/2Y

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46
TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 37 of 46
NXP Semiconductors
TEA19161T
Digital controller for high-efficiency resonant power supply
V
uvp(SUPREG)
undervoltage protection
voltage on pin SUPREG
8.6 9.0 9.4 V
SNSCAP pin
V
AV(regd)SNSCAP
regulated average voltage
on pin SNSCAP
regulated average of V
hs(SNSCAP)
and V
ls(SNSCAP)
-2.50-V
I
bias(max)SNSCAP
maximum bias current on
pin SNSCAP
245 210 175 A
V
th(max)SNSCAP
maximum threshold voltage
difference on pin SNSCAP
V
hs(SNSCAP)
V
ls(SNSCAP)
;
P
out
=200%; V
SNSBOOST
=2.5V
-1.92-V
V
hs(SNSCAP)
V
ls(SNSCAP)
;
P
out
=200%; V
SNSBOOST
<2.0V
2.85 3.00 3.15 V
Overpower protection
V
opp(SNSCAP)
overpower protection
voltage difference on pin
SNSCAP
V
hs(SNSCAP)
V
ls(SNSCAP)
;
P
out
= 150 %; V
SNSBOOST
=2.5V
-1.44-V
V
hs(SNSCAP)
V
ls(SNSCAP)
;
P
out
= 150 %; V
SNSBOOST
=2.1V
-2.24-V
t
PD(SNSCAP)
propagation delay on pin
SNSCAP
from crossing
V
ls(SNSCAP)
/V
hs(SNSCAP
) level to
GATELS/GATEHS switch-off
-150-ns
t
d(opp)
overpower protection delay
time
See Table 5 for related R
SNSSET1
40 50 60 ms
See Table 5
for related R
SNSSET1
160 170 180 ms
t
d(restart)
restart delay time 0.8 1.0 1.2 s
SNSCUR pin
V
bias(SNSCUR)
bias voltage on pin
SNSCUR
2.4 2.5 2.6 V
R
O(SNSCUR)
output resistance on pin
SNSCUR
-60-k
V
ocp
overcurrent protection
voltage
positive level;
V
SNSCUR
V
bias(SNSCUR)
1.35 1.50 1.65 V
negative level;
V
SNSCUR
V
bias(SNSCUR)
1.65 1.50 1.35 V
V
reg(capm)
capacitive mode regulation
voltage
positive level;
V
SNSCUR
V
bias(SNSCUR)
85 100 115 mV
negative level;
V
SNSCUR
V
bias(SNSCUR)
115 100 85 mV
V
det(zero)
zero detection voltage detected as 0-13 - mV
detected as 0-13-mV
SNSBOOST pin
V
start(SNSBOOST)
start voltage on pin
SNSBOOST
2.2 2.3 2.4 V
V
uvp(SNSBOOST)
undervoltage protection
voltage on pin SNSBOOST
1.5 1.6 1.7 V
V
det(SNSBOOST)
detection voltage on pin
SNSBOOST
when below power good = LOW - 1.95 - V
Table 9. Characteristics
…continued
T
amb
=25
C; V
SUPIC
= 19.5 V; all voltages are measured with respect to GND; currents are positive when flowing into the IC;
unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 38 of 46
NXP Semiconductors
TEA19161T
Digital controller for high-efficiency resonant power supply
PFC burst mode controller
en(burst)
burst mode enable duty
cycle
enable of PFC burst mode;
duty cycle of LLC burst mode
-50-%
N
cy(en)burst
burst mode enable number
of cycles
enable of PFC burst mode;
cycles of LLC burst mode
-8-
dis(burst)
burst mode disable duty
cycle
disable of PFC burst mode;
duty cycle of LLC burst mode
-75-%
V
pu(SNSBOOST)
pull-up voltage on pin
SNSBOOST
to enter PFC burst mode off-state - 2.95 - V
I
off(burst)
burst mode off-state current during PFC burst mode off-state 7.1 6.4 5.7 A
V
off(burst)
burst mode off-state voltage
difference
during PFC burst mode off-state;
between peak voltage and end of
off-state
- 75 - mV
V
on(burst)max
maximum burst mode
on-state voltage
during PFC burst mode on-state 2.29 2.37 2.45 V
t
to(det)on(burst)
burst mode on-state
detection time-out time
during PFC burst mode on-state 3.7 4.0 4.3 ms
PFC protection controller
R
pd(SNSBOOST)
pull-down resistance on pin
SNSBOOST
at protection activation - 550 -
I
pd(SNSBOOST)
pull-down current on pin
SNSBOOST
during active protection 94 110 127 A
I
prot(SNSBOOST)
protection current on pin
SNSBOOST
-60-nA
SNSOUT pin
V
ovp(SNSOUT)
overvoltage protection
voltage on pin SNSOUT
3.36 3.50 3.64 V
I
prot(SNSOUT)
protection current on pin
SNSOUT
for open pin - 60 - nA
SNSFB pin
V
bias(SNSFB)
bias voltage on pin SNSFB I
SNSFB
= 85 A2.22.52.8V
Optobias regulator
I
reg(SNSFB)
regulation current on pin
SNSFB
I
start(burst)
= 106 A;
tracks with I
start(burst)
- 85 - A
I
reg(max)SNSFB
maximum regulation current
on pin SNSFB
I
start(burst)
= 106 A;
tracks with I
start(burst)
- 310 - A
I
reg(min)SNSFB
minimum regulation current
on pin SNSFB
I
start(burst)
= 106 A;
tracks with I
start(burst)
- 63 - A
Burst mode regulator
I
start(burst)
burst mode start current LLC burst mode 123 106 89 A
I
stop(burst)
burst mode stop current LLC burst mode - 200 - A
Table 9. Characteristics …continued
T
amb
=25
C; V
SUPIC
= 19.5 V; all voltages are measured with respect to GND; currents are positive when flowing into the IC;
unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
TEA19161T All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet Rev. 1 — 10 March 2016 39 of 46
NXP Semiconductors
TEA19161T
Digital controller for high-efficiency resonant power supply
GATELS and GATEHS pins
I
source(GATEHS)
source current on pin
GATEHS
V
GATEHS
V
HB
=4V - 340 - mA
I
source(GATELS)
source current on pin
GATELS
V
GATELS
V
GND
=4V - 340 - mA
I
sink(GATEHS)
sink current on pin GATEHS V
GATEHS
V
HB
= 2 V - 580 - mA
V
GATEHS
V
HB
=11V - 2 - A
I
sink(GATELS)
sink current on pin GATELS V
GATELS
V
GND
= 2 V - 580 - mA
V
GATELS
V
GND
=11 V - 2 - A
V
rst(SUPHS)
reset voltage on pin SUPHS 6.4 7 7.6 V
V
rst(hys)SUPHS
hysteresis of reset voltage
on pin SUPHS
>V
rst(SUPHS)
-0.6-V
t
on(min)
minimum on-time - 0.83 - s
t
on(max)
maximum on-time 14.8 17.4 20.0 s
t
sweep
sweep time frequency; at start-up 1 12 14 ms
Low-power mode regulator
f
lp(min)
minimum low-power mode
frequency
20 23 26 kHz
Burst mode regulator
f
burst(max)
maximum burst mode
frequency
R
SNSOUT1
=22k 170 200 230 Hz
R
SNSOUT1
=15k 340 400 460 Hz
R
SNSOUT1
=10k 680 800 920 Hz
R
SNSOUT1
=6.8k 1360 1600 1840 Hz
Power good characteristics (pin SNSSET)
V
OH(SNSSET)
HIGH-level output voltage
on pin SNSSET
I
SNSSET
= 100 A;
power good = LOW
-4-V
I
OH(SNSSET)
HIGH-level output current
on pin SNSSET
V
SNSSET
=3V;
power good = LOW
11 8 5mA
I
OL(SNSSET)
LOW-level output current on
pin SNSSET
V
SNSSET
=0.5V;
power good = HIGH
81114mA
t
d(H)SNSSET
HIGH-level delay time on
pin SNSSET
See Table 5 for related R
SNSSET1
35 45 55 ms
See Table 5
for related R
SNSSET1
150 190 230 ms
Settings sensor (SNSOUT, SNSSET, and GATELS pins)
I
O(SNSOUT)
output current on pin
SNSOUT
during R
SNSOUT1
measurement - 171 - A
I
O(SNSSET)
output current on pin
SNSSET
during R
SNSSET
measurement - 26.8 - A
V
O(GATELS-SUPREG)
output voltage difference
between pin GATELS and
pin SUPREG
during R
GATELS
measurement - 1.25 - V
Table 9. Characteristics
…continued
T
amb
=25
C; V
SUPIC
= 19.5 V; all voltages are measured with respect to GND; currents are positive when flowing into the IC;
unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P46

TEA19161T/2Y

Mfr. #:
Buy TEA19161T/2Y
Manufacturer:
NXP Semiconductors
Description:
Switching Controllers TEA19161T/SO16//2/REEL 13 Q1 DP
Lifecycle:
New from this manufacturer.
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