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ICS932S203AFLNT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18
IDT
TM
Frequency Generator with 133MHz Differential CPU Clocks 0601G—01/26/10
ICS932S203
Frequency Generator with 133MHz Differential CPU Clocks
4
Byte 0: Control Register
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
3. The purpose of this bit is to allow a system designer to implement PCI_STOP functionality in one of two ways. Wither the
system designer can choose to use the externally provided PCI_STOP# pin to assert and de-assert PCI_STOP
functionality via SMBus Byte 0 Bit 3.
In Hardware mode it is not allowed to write to the SMBus Byte 0 Bit3. In Software mode it is not allowed to pull the
external PCI_STOP pin low. This avoids the issues related with Hardware started and software stopped PCI_STOP
conditions. The clock chip is to be operated in the Hardware or Software PCI_STOP mode ONLY, it is not allowed to mix
these modes.
In Hardware mode the SMBus byte 0 Bit 3 is R/W and should reflect the status of the part. Whether or not the chip is in
PCI_STOP mode.
Functionality PCI_STOP mode should be entered when [(PCI_STOP#=0) or (SMBus Byte 0 Bit 3 = 0)].
Byte 1: Control Register
tiB#niPemaNDWPepyTnoitpircseD
0tiB- 1 )devreseR(
1tiB550SFXR purewopnodelpmasnip0SFfoeulavehtstcelfeR
2tiB041SFXR purewopnodel
pmasnip1SFfoeulavehtstcelfeR
3tiB43#POTS_ICP
3
XR
#POTS_ICPfoeulavehtstcelfeR:edomerawdraH
DWPnodelpmasnip
4tiB- 1 )devreseR(
5tiB53HCV/1_66V30WR
zHM84/zHM66tceleS
HCV
zHM84=1,zHM66=0
6tiB- 0 )devreseR(
7tiB-
daerpS
delbanE
0WRnOdaerpS=1,ffOdaerpS=0
tiB#niPemaNDWPepyTnoitpircseD
0tiB15,25
0TKLCUPC
0CKLCUPC
1WRdelbanE=1delbasiD=0
1tiB84,94
1TKLCUPC
1CKLCUPC
1WRdelbanE=
1delbasiD=0
2tiB44,54
2TKLCUPC
2CKLCUPC
1WRdelbanE=1delbasiD=0
3tiB15,250-devreseR
4tiB84,940-devreseR
5tiB44,540-devreseR
6
tiB45,35
3TKLCUPC
3CKLCUPC
1WRdelbanE=1delbasiD=0
7tiB340LESTLUMXR 0LESTLUMfoeulavtnerrucehtstcelfeR
IDT
TM
Frequency Generator with 133MHz Differential CPU Clocks 0601G—01/26/10
ICS932S203
Frequency Generator with 133MHz Differential CPU Clocks
5
Byte 2: Control Register
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
tiB#niPemaNDWPepyTnoitpircseD
0tiB010KLCICP1WRdelbanE=1delbasiD=0
1tiB111KLCICP1WRdelbanE=1delbasiD=0
2tiB212KLCICP1WRdelban
E=1delbasiD=0
3tiB313KLCICP1WRdelbanE=1delbasiD=0
4tiB614KLCICP1WRdelbanE=1delbasiD=0
5tiB715KLCICP1WRdelbanE=1delbasiD
=0
6tiB816KLCICP1WRdelbanE=1delbasiD=0
7tiB- - 0 - )devreseR(
Byte 3: Control Register
Byte 4: Control Register
tiB#niPemaNDWPepyTnoitpircseD
0tiB122-66V3/0TUO_zHM661WRdelbanE=1delbasiD=0
1tiB223-66V3/0TUO_zHM661WRdelbanE=1delbasi
D=0
2tiB324-66V3/0TUO_zHM661WRdelbanE=1delbasiD=0
3tiB425_66V31WRdelbanE=1delbasiD=0
4tiB53KLC_HCV/1_66V31WRdelbanE=1de
lbasiD=0
5tiB330_66V31WRdelbanE=1delbasiD=0
6tiB- - 0 R )devreseR(
7tiB- - 0 R )devreseR(
tiB#niPemaNDWPepyTnoitpircseD
0tiB5 0F_KLCICP1WRdelbanE=1delbasiD=0
1tiB6 1F_KLCICP1WRdelbanE=1delbasiD=0
2tiB7 2F_KLCICP1WRdel
banE=1delbasiD=0
3tiB5 0F_KLCICP0WR
fonoitressahtiw0F_KLCICPfolortnocwollA
gninnureerftoN=1,gninnuReerF=0.#PO
TS_ICP
4tiB6 1F_KLCICP0WR
fonoitressahtiw1F_KLCICPfolortnocwollA
gninnureerftoN=1,gninnuReerF=0.#POTS_ICP
5tiB7 2
F_KLCICP0WR
fonoitressahtiw2F_KLCICPfolortnocwollA
gninnureerftoN=1,gninnuReerF=0.#POTS_ICP
6tiB93BSU_zHM841WRd
elbanE=1delbasiD=0
7tiB83TOD_zHM841WRdelbanE=1delbasiD=0
IDT
TM
Frequency Generator with 133MHz Differential CPU Clocks 0601G—01/26/10
ICS932S203
Frequency Generator with 133MHz Differential CPU Clocks
6
Byte 6: Vendor ID Register
(1 = enable, 0 = disable)
tiB#niPemaNDWPepyTnoitpircseD
0tiBX 0tiBDIrodneV1R)devreseR(
1tiBX 1tiBDIrodneV0R)devreseR(
2tiBX 2tiBDIrodneV0R)devreseR(
3tiBX 3t
iBDIrodneV0R)devreseR(
4tiBX 0tiBDInoisiveRXR
nodesabeblliwseulavDInoisiveR
noisivers'ecivedlaudividni
5tiBX 1tiBDInoisiveRXR
6tiBX 2tiBDInoisiveRXR
7tiBX 3tiBDInoisiveRXR
Byte 5: Programming Edge Rate
(1 = enable, 0 = disable)
Notes:
1. R= Read only RW= Read and Write
2. PWD = Power on Default
tiB#niPemaNDWPepyTnoitpircseD
0tiBX BSU_zHM840WRlortncetaregdeBSU
1tiBX BSU_zHM840WRlortncetaregdeBSU
2tiBX TOD_zHM840WRlortnoc
etaregdeTOD
3tiBX TOD_zHM840WRlortnocetaregdeTOD
4tiBX - 0 - )devreseR(
5tiBX - 0 - )devreseR(
6tiBX - 0 - )devreseR(
7tiBX - 0 - )devreseR(
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18

ICS932S203AFLNT

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Manufacturer:
Description:
IC FREQ GEN W/CPU CLOCK 56-SSOP
Lifecycle:
New from this manufacturer.
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