NCP12700
www.onsemi.com
15
attenuated COMP voltage when the switching duty cycle is
nominally 40% and reduces the voltage by a peak, V
SLP(PK)
,
of 98 mV at the 80% duty cycle limit. The slope
compensating ramp is synchronized to the duty cycle of the
oscillator, effectively adjusting itself based on the switching
frequency, providing the converter with a compensating
dv/dt ramp appropriate for the particular switching
frequency. An image of the slope compensating ramp is also
applied at the input of the Current Limit comparator to
prevent sub−harmonic oscillations from occurring during
overload conditions. The chart below summarizes the dv/dt
of the compensating ramp at some common operating
frequencies.
F
SW
(kHz)
T
SW
(ms) D = 40% (ms) D = 80% (ms)
V
SLP
(mV)
Ramp (mV/ms)
100 10.00 4.00 8.00 98 25
200 5.00 2.00 4.00 98 49
250 4.00 1.60 3.20 98 61
330 3.03 1.21 2.42 98 81
400 2.50 1.00 2.00 98 98
500 2.00 0.80 1.60 98 123
Cycle−by−Cycle Current Limit and Overload Protection
The NCP12700 implements cycle−by−cycle current
limiting with a dedicated Current Limit Comparator. The
input to the comparator is the primary FET current ramp
sensed at the CS pin. If the sensed voltage exceeds the
current limit threshold, V
CS(LIM)
, of 495 mV then the drive
pulse is terminated. The Current Limit Comparator is very
fast with a total propagation delay, t
CS(DLY)
, of 75 ns
maximum ensuring that drive pulses are quickly terminated
minimizing current overshoot in the converter.
The Current Limit comparator also triggers an overload
timer, t
CS(OVLD)
, nominally 30 ms, and will disable drive
pulses and take the device into a Fault mode when the timer
has expired. The 30 ms timer allows the converter to sustain
a short term overload but still protects the converter from
thermal overstress in the event of a continuously applied
overload condition. The overload timer is also an integrating
timer, it will continue ramping up while the Current Limit
Comparator is terminating drive pulses but will begin
ramping down, not reset completely, if the drive pulse is
terminated by another signal such as the PWM comparator.
This operation is depicted in Figure 11.
Figure 11. Integrating Overload Timer
V
COMP
V
DRV
Overload
Timer
time
t
1
t
2
t
3
t
4
t
5
t
6
Short Circuit (SCP) Comparator
The NCP12700 also includes a fast Short Circuit
Comparator with a threshold, V
SCP(LIM)
, of 625 mV. In
certain extreme fault conditions such as a shorted secondary
side rectifier or a shorted winding in the transformer it may
be possible to sense an abnormally high current pulse at the
CS pin and disable drive pulses to prevent the converter from
