NCP12700
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16
further damage. If the voltage at the CS pin rapidly exceeds
625 mV and the SCP comparator trips, then the drive pulse
will be terminated and a counter will be incremented. If the
SCP comparator trips on 4 consecutive drive pulses then
drive pulses will be disabled and the controller is put into the
Fault mode.
Leading Edge Blanking (LEB)
Converters operating in peak current mode control require
a high quality current ramp signal to ensure stable and clean
PWM operation. In the NCP12700 the current ramp signal
is sensed at the CS pin and is routed through a LEB circuit
which blanks the current sense information for a brief period
after the DRV voltage is delivered to the primary MOSFET.
The LEB prevents noise generated during the switching
transition from terminating drive pulses prematurely. The
blanking is performed by an internal pulldown switch and
series disconnect switch. The internal pulldown switch has
an on resistance, R
PD(LEB)
, specified as 55 ohms maximum.
The pulldown switch is turned on whenever the DRV is low
and remains on for a period of time equal to t
LEB(SCP)
, 60 ns
typical, after the DRV is set high.
After t
LEB(SCP)
has expired the current ramp signal is
delivered to the SCP comparator allowing it to sense an
abnormal overcurrent situation. A longer series LEB,
t
LEB(CS)
, of 100 ns continues to hold open the signal path to
the CS and PWM comparators. This switch closes when
t
LEB(CS)
has expired, allowing the CS information to be
delivered to the other two comparators. In addition to the
LEB network, the user of the controller will usually place a
small RC filter in between the current sense components and
the CS pin to provide noise suppression. The resistor value
in the RC filter is typically in the range of 500 – 1 kW, sized
appropriately for the Over−Power protection feature, and
the capacitor value is typically chosen to provide a time
constant for the RC filter of about 50 – 100 ns.
Skip Comparator
For a power converter operating at light loads it is
sometimes desired to skip drive pulses in order to maintain
output voltage regulation or improve the light load
efficiency of the system. The NCP12700 features a
dedicated Skip Comparator which monitors the voltage at
the COMP pin and blanks drive pulses if the COMP voltage
falls below the V
COMP(skip)
threshold of 300 mV. To
re−enable new drive pulses, the COMP voltage must exceed
a skip hysteresis, V
COMP(skip_hys)
of 25 mV above the
300 mV threshold. The skip hysteresis is designed to
prevent the converter from oscillating in and out of skip
mode due to noise on the COMP pin.
Maximum Duty Cycle
The NCP12700 also includes a maximum duty cycle
clamp which terminates a drive pulse which has been high
for D
MAX
of the switching period. The default value of
D
MAX
will be 80%.
Soft Start
The soft start feature in the NCP12700 is implemented
with a dedicated comparator that compares the current ramp
signal from the CS pin against an attenuated soft start ramp
generated at the SS pin. Prior to enabling switching, an
internal pull−down transistor with an on resistance,
R
SS(DIS)
, of 100 W is activated to discharge the external soft
start capacitor and hold the SS pin to GND. Once switching
is enabled the pull−down transistor is released and a current
source, I
SS
, of 15 mA charges the soft start capacitor forming
the soft start ramp voltage. The soft start ramp voltage is then
divided down by a factor of 6 and fed into the soft start
comparator which resets drive pulses when the CS voltage
exceeds the soft start voltage. The soft start comparator will
continue to reset drive pulses until another comparator
enters the reset path which typically occurs when the
secondary side control loop responds allowing the PWM
comparator to take control.
The NCP12700 monitors the external soft start voltage
and sets a flag when the voltage exceeds 3 V, declaring that
the soft start period has ended. At 3 V, the drive pulse reset
control will have been handed off to either the PWM
comparator or the Current limit comparator. The SS_END
flag is used internally by the controller for fault
management, gating detection of certain faults that may be
erroneously triggered during power up of the converter. This
is shown in the FLT pin block diagram of Figure 12.
Figure 12. FLT Pin Block Diagram
VDD
V
FLT(OTP)
SS_END
I
FLT
To Fault Logic
V
FLT(OVP)
V
FLT(OTP_HYS)
t
OTP(DLY)
t
OVP(DLY)
To V
CC
NCP12700
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17
Fault (FLT) Pin
The FLT pin is intended to provide the system with a NTC
interface for thermal protection and a pull−up fault which
can be coupled to the auxiliary winding to provide output
over−voltage protection. The FLT pin can also be used as a
general purpose fault where it interfaces with a simple
pull−down BJT, open collector comparator, or optocoupler
for monitoring of secondary side faults. The internal
circuitry includes a precision pull−up current source, I
FLT
, of
85 mA and a window comparator to signal a fault whenever
the pin voltage goes below the OTP fault threshold,
V
FLT(OTP)
, of 0.5 V or above the OVP fault threshold,
V
FLT(OVP)
, of 3 V. Both of the fault comparators also include
a delay filter to prevent noise or glitches from setting the
fault. The over−temperature fault filter, t
OTP(DLY)
, is
nominally 20 ms and the over−voltage fault filter, t
OVP(DLY)
,
is typically 5 ms. An external filter capacitor is also
advisable.
Both faults have an option to permanently latch off the
controller or restart after a 1 s auto−recovery period. The
OVP fault is intended to monitor an auxiliary winding and
when triggered, the controller will disable switching which
will inhibit the aux winding from generating voltage and
allow the controller to restart after the auto−recovery timer
has expired. If the OVP fault comparator is continuously
held above 3 V, the NCP12700 will remain in the fault mode
and not restart.
The OTP fault detection is gated by the SS_END flag to
prevent the comparator from triggering while the external
filter capacitor charges up. Once the SS_END flag is set the
OTP fault can be acknowledged so there is a practical limit
on the size of the filter capacitor. Equation 6 and Equation 7
should assist the user with properly setting the external
capacitance of the fault pin.
t
SS_END
+
C
SS
V
SS_END
I
SS
(eq. 6)
C
FLT
t
I
FLT
t
SS_END
V
FLT(OTP)
(eq. 7)
When the OTP fault is triggered the NCP12700 will again
disable drive pulses and transition into a fault mode. The
OTP fault is auto−recoverable based on the auto−recovery
timer and a hysteresis set by the V
FLT(REC)
threshold of
0.9 V. The auto−recovery timer must expire and the voltage
at the fault pin must exceed 0.9 V. This methodology
guarantees a minimum amount of time for the system to
recover from thermal overstress but will not allow the
converter to restart unless the hysteresis is met. Given the
I
FLT
and V
FLT(OTP)
specifications the critical NTC
resistance for declaring a fault is ~ 5.9 kW. The critical
resistance for recovering from the OTP fault becomes ~
10.6 kW. This fault recovery threshold provides for about
~20°C of hysteresis for many NTC resistors.
Summary of Fault Handling
The NCP12700 has 6 fault detectors which will place the
device into the fault mode. In the fault mode switching is
inhibited and the controller bias is maintained by the HV
startup regulator. The controller also reduces current
consumption to I
CC(FLT)
, 500 mA maximum, so that the
regulator is not thermally overstressed. The NCP12700
remains in the fault mode until the fault signal has been
cleared and/or the auto−recovery timer has expired. The
fault signal can be cleared when the fault detector senses that
the fault has been removed or by a controller reset which
occurs if V
CC
drops below V
CC(OFF)
or the UVLO pin is
pulled below the V
RST(th)
level. Below is a brief summary
of the different fault detectors and their basic operation.
Thermal Shutdown (TSD): Thermal shutdown is
declared when the internal junction temperature of the
device exceeds the T
SHDN
temperature of 165°C. The
thermal shutdown fault is auto−recoverable when the
device junction temperature reduces to T
SHDN
T
SHDN(hys)
where T
SHDN(hys)
is typically 25°C.
Fault OTP: An OTP fault is declared when fault pin
voltage decreases below the V
FLT(OTP)
threshold of
0.5 V and the OTP filter, t
OTP(DLY)
, expires. The OTP
filter delay is typically 20 ms. The OTP fault is blanked
at startup until the SS_END flag has been set to allow
the external capacitance of the pin to charge up. For the
device to recover from the Fault OTP, the
auto−recovery timer must expire and the voltage at the
fault pin must recover to V
FLT(REC)
value of 0.9 V.
Fault OVP: The OVP fault is declared when fault pin
the voltage exceeds the V
FLT(OVP)
threshold of 3 V and
the OVP filter, t
OVP(DLY)
, expiring. The OVP filter
delay is typically 5 ms. The OVP fault is cleared when
the auto−recovery timer expires. There is no hysteresis
on the OVP fault but if the pin voltage is permanently
held above 3 V, DRV will pulses will be permanently
inhibited.
Overload (OVLD): The OVLD fault is set when the
overload timer, t
OVLD
, expires. The overload timer is
an integrating timer which counts up as long as the
Current Limit comparator is terminating DRV pulses.
The typical value for t
OVLD
is 30 ms. The controller
will recover from the OVLD fault when the
auto−recovery timer expires.
SCP Fault: The SCP fault occurs when the N
SCP
counter has reaches 4 consecutive DRV pulses
terminated by the SCP comparator. The controller will
recover from the SCP fault when the auto−recovery
timer expires.
V
CC
OVP: The V
CC
OVP is set when V
CC
voltage
exceeds the V
CC(OVP)
threshold of 28 V and the V
CC
OVP filter, t
VCC_OVP(DLY)
, expires. The V
CC
OVP
filter is typically 3 ms. V
CC
OVP will permanently latch
the device off so that it remains in the Fault mode
indefinitely until the controller is reset.
NCP12700
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18
Evaluation Board Designs
Two evaluation boards have been developed to highlight
the features of the NCP12700. Detailed schematics,
operating waveforms, and bill of materials are available in
the design notes, DN05108 and DN05109. DN05108
describes the operation of a 9 – 36 V input flyback converter
delivering 12 V out at 15 W. This evaluation board switches
at 200 kHz and operates in both continuous and
discontinuous conduction modes. The key performance
specifications are shown in Table 5 below.
Table 5. LOW VOLTAGE FLYBACK EVALUATION
BOARD SPECIFICATIONS
Evaluation Board # 1
Vin 9 − 36 V Operating
Vo 12 V − 1.25 A
Po 15 W
Specifications
Startup time < 30 ms
Full Load Efficiency > 87 %
Transient Response
< 250 ms
Over Power Protection 120% − 150%
Over Voltage Protection 16 VDC Max
No Load Output Ripple 200 mVpp Max
No Load Power Dissipation 120 mW Max
Input Current in SHDN < 1 mA
DN05109 describes the operation of a 18 – 160 V input
flyback converter delivering 12 V out at 15 W. This
demonstration board switches at 100 kHz and operates in
discontinuous conduction mode across the entire input
voltage range. The key performance specifications are
shown in Table 6.
Table 6. WIDE RANGE FLYBACK EVALUATION
BOARD SPECIFICATIONS
Evaluation Board # 2
Vin 18 − 160 V Operating
Vo 12 V − 1.25 A
Po 15 W
Specifications
Startup time < 20 ms
Full Load Efficiency > 85 %
Transient Response
< 250 ms
Over Power Protection 115% − 155%
Over Voltage Protection 16 VDC Max
No Load Output Ripple 150 mVpp Max
No Load Power Dissipation 500 mW Max
Input Current in SHDN < 1 mA

NCP12700ADNR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Switching Controllers CURRENT MODE PWM CONTROLL
Lifecycle:
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