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NCP12700ADNR2G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20
NCP12700
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4
VIN
VCC
DRV
GND
CS
UVLO
FLT
SS
RT
COMP
VIN
VCC
DRV
GND
CS
UVLO
FLT
SS
RT
COMP
PINOUTS
(Top Views)
EP
Table 1. PIN FUNCTION DESCRIPTION
MSOP10 WQFN10 Pin Name Pin Description
1 9 UVLO The UVLO pin is the input to the Standby and UVLO comparators. A resistor divider between
the power supply input voltage and ground is connected to the UVLO pin to set the input volt-
age level at which the controller will be enabled. UVLO Hysteresis is set by a 5 mA pull−down
current source. An externally supplied pull−down signal can also be used to disable the con-
troller. The UVLO pin is also used to determine the Over−Power Protection current supplied to
the CS pin.
2 10 FLT The FLT pin is the input to a window comparator which provides an upper and lower fault
threshold. When either threshold is tripped, the controller enters the fault mode which can be a
permanent latch off or a minimum 1 s auto−recovery period. A precision current source is out-
put from the FLT pin allowing an NTC to ground to be placed at the pin for system Over−tem-
perature protection. The upper threshold can be used for output over−voltage protection
sensed through the auxiliary winding or as a general purpose fault.
3 1 SS The SS pin sets the soft−start ramp of the peak current limit when the controller is enabled. An
internal 15 mA current source and an external capacitor to ground are used to control the ramp
rate. Typical soft start capacitor values will be in the range of 10 nF to 100 nF.
4 2 RT The RT pin sets the oscillator frequency in the controller. This pin requires a resistor to ground
located close to the IC. Typical RT values are in the range of 10 kW – 100 kW.
5 3 COMP The COMP pin provides the compensated error voltage for the PWM and Skip comparators.
An internal 5 kW pull−up resistor is connected to the COMP pin and can be used to bias the
transistor of an opto−coupler.
6 4 CS The CS pin is the current sense input for the PWM and Current Limit comparators. The com-
parator input is held low for 60 ns after the DRV goes high to prevent leading edge current
spikes from tripping the comparators. An external low pass filter is recommended for improved
noise immunity. The external filter resistor is also used to determine the amount of Over−Pow-
er Protection applied to the current sense.
7 5 GND This pin is the controller ground. For the WQFN package the exposed pad (EP) should be
connected to GND.
8 6 DRV The DRV pin is a high current output used to drive the external MOSFET gate. DRV has
source and sink capability of 1 A and 2.8 A, respectively.
9 7 VCC The VCC pin provides bias to the controller. An external decoupling capacitor to ground in the
range of 1 – 10 mF is recommended.
10 8 VIN The VIN pin is the input to the high voltage startup regulator. The regulator is capable of sourc-
ing > 15 mA to temporarily bias VCC while the application is starting up.
ORDERING INFORMATION
Device Package OTP Fault OVP Fault Shipping
†
NCP12700ADNR2G MSOP10 Latch Latch 4000 / Tape & Reel
NCP12700BDNR2G MSOP10 Autorecovery Autorecovery 4000 / Tape & Reel
NCP12700BMTTXG WQFN10 Autorecovery Autorecovery 3000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specification Brochure, BRD8011/D.
NCP12700
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5
Table 2. MAXIMUM RATINGS
Rating Symbol Value Unit
High Voltage Startup Voltage (MSOP10)
(WQFN10)
V
IN(MAX)
120
200
V
High Voltage Startup Current I
IN(MAX)
50 mA
Supply Voltage V
CC(MAX)
−0.3 to 30 V
Supply Current I
CC(MAX)
50 mA
DRV Voltage (Note 1) V
DRV(MAX)
−0.3 V to V
DRV(high)
V
DRV Current (Peak) I
DRV(MAX)
3.25 A
FLT Voltage V
FLT(MAX)
V
CC
+ 1.25 V
FLT Current I
FLT(MAX)
10 mA
Max Voltage on Signal Pins V
SIG(MAX)
−0.3 to 5.5 V
Max Current on Signal Pins I
SIG(MAX)
10 mA
Thermal Resistance Junction−to−Air (Note 2) (MSOP10)
(WQFN10)
R
θ
J−A
165
51
°C/W
Junction−to−Top Thermal Characterization Parameter (MSOP10)
(WQFN10)
Y
J−C
10
12
°C/W
Maximum Junction Temperature T
JMAX
150 °C
Maximum Power Dissipation (MSOP10)
(WQFN10)
P
D
Internally Limited W
Storage Temperature Range T
STG
−55 to 150 °C
Operating Temperature Range T
J
−40 to 125 °C
ESD Capability (Note 3)
Human Body Model per JEDEC Standard JESD22−A114E
Charge Device Model per JEDEC Standard JESD22−C101E
2000
1000
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. Maximum driver voltage is limited by the driver clamp voltage, V
DRV(high)
, when V
CC
exceeds the driver clamp voltage. Otherwise, the
maximum driver voltage is V
CC
.
2. Per JEDEC specification JESD51.7 using two 1 oz copper planes with board size = 80x80x1.6 mm
3. This device series contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per JEDEC Standard JESD22−A114E
Charge Device Model TBD per JEDEC Standard JESD22−C101E
4. This device contains latch−up protection and has been tested per JEDEC JESD78D, Class I and exceeds +/−100 mA (TBD).
Table 3. RECOMMENDED OPERATING CONDITIONS
Rating Symbol Value Unit
VIN Voltage (MSOP10)
(WQFN10)
V
IN
9 – 100
12 – 160
V
Supply Voltage − All V
CC
9 – 20 V V
Operating Temperature Range T
J
−40 to 125 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
NCP12700
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6
Table 4. ELECTRICAL CHARACTERISTICS (V
IN
= 12 V, V
CC
= 12 V, V
COMP
= Open, V
FLT
= Open, C
DRV
= 1 nF, R
T
= 49.9k
,
V
CS
= 0 V, V
SS
= Open, V
UVLO
= 1.2, for typical values T
J
= 25°C, for min/max values, T
J
is – 40°C to 125°C, unless otherwise noted)
Characteristics
Test Condition Symbol Min Typ Max Unit
HIGH VOLTAGE STARTUP REGULATOR
Regulated Voltage V
CC
= Open, I
CC
= 5 mA V
CC(REG)
7.6 8 8.4 V
Current Source Capability V
IN
= 9 V, V
CC
= 7 V I
VIN(SRC)
15 mA
Current Source Limit V
CC
= V
CC(off)
+ 100 mV I
VIN(LIM)
30 mA
Off−State Leakage Current (xMTTXG) V
CC
= Open, V
IN
= 160 V, V
UVLO
= 0 I
VIN(OFF)
100
mA
Off−State Leakage Current (xDNR2G) V
CC
= Open, V
IN
= 120 V, V
UVLO
= 0 I
VIN(OFF)
100
mA
SUPPLY CIRCUIT
Supply Voltage
Startup Threshold
Minimum Operating Voltage
V
CC
increasing
V
CC
decreasing
V
CC(on)
V
CC(off)
V
CC(REG)
–
350 mV
6.2
6.5
V
CC(REG)
–
100 mV
6.8
V
Supply Over−Voltage Protection V
CC(OVP)
28 V
VCC OVP Detection Filter Delay t
VCCOVP
(DLY)
3
ms
Startup Delay Measured from V
CC(ON)
to SS t
ON(Dly)
25
ms
Supply Current
SHDN
STBY
Enable
Fault
V
UVLO
= 0 V
V
UVLO
= 0.7 V
C
DRV
= Open, V
COMP
= 2 V
V
FLT
= 0 V
I
CC(SHDN)
I
CC(STBY)
I
CC(EN)
I
CC(FLT)
−
−
−
−
−
−
−
−
50
750
4
500
mA
mA
mA
mA
CURRENT SENSE
Current Limit Comparator Threshold
V
CS(LIM)
465 495 525 mV
Propagation Delay From Current
Sense Limit to DRV Low
Step V
CS
from 0 – 0.6 V t
CS(DLY)
− − 75 ns
Short Circuit Protection (SCP) Current
Limit Threshold
V
SCP(LIM)
625 mV
Propagation Delay From Short Circuit
Limit to DRV Low
V
CS
= 0.75 V t
SCP(DLY)
− − 75 ns
Short Circuit Counter V
CS
= 0.75 V N
SCP
4
CS Leading Edge Blanking (LEB) t
LEB(CS)
75 100 125 ns
SCP Leading Edge Blanking t
LEB(SCP)
45 60 75 ns
CS LEB Pull−down Resistance R
PD(LEB)
− 55
W
Overload Timer Duration V
CS
= 0.6 V t
CS(OVLD)
24 30 36 ms
Applied Slope Compensation @ Cur-
rent Limit Comparator
V
COMP
= Open; Measured at D
80%
V
SLP(ILIM)
83 102 123 mV
Duty Cycle Where Slope Compensat-
ing Ramp Begins
D
40%
40 %
COMP SECTION
PWM to COMP Gain Through Resistor
Divider
V
COMP
= 2 V K
PWM
6
PWM Propagation Delay to DRV Low V
COMP
= 2 V, Step from CS 0– 0.4 V t
PWM(Dly)
− 75 ns
COMP Open Pin Voltage V
COMP(open)
4 4.7 V
COMP Output Current V
COMP
= 0 I
COMP
0.84 1 1.2 mA
Maximum Duty Cycle V
COMP
= Open D
MAX
76 80 84 %
COMP Skip Threshold V
COMP(skip)
300 mV
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P20

NCP12700ADNR2G

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Manufacturer:
ON Semiconductor
Description:
Switching Controllers CURRENT MODE PWM CONTROLL
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