1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2009, Zarlink Semiconductor Inc. All Rights Reserved.
Features
Supports AT&T TR62411 and Bellcore GR-1244-
CORE and Stratum 4 timing for DS1 interfaces
Supports ETSI ETS 300 011, TBR 4, TBR 12 and
TBR 13 timing for E1 interfaces
Selectable 19.44 MHz, 1.544 MHz, 2.048 MHz or
8kHz input reference signals
Provides C1.5, C2, C4
, C6, C8, C16, and C19
(STS-3/OC3 clock divided by 8) output clock
signals
Provides 5 different styles of 8 KHz framing
pulses
Attenuates wander from 1.9 Hz
Fast lock mode
JTAG Boundary Scan
Applications
Synchronization and timing control for multitrunk
T1 and E1 systems
ST-BUS clock and frame pulse source
Description
The MT9040 T1/E1 System Synchronizer contains a
digital phase-locked loop (DPLL), which provides timing
and synchronization signals for T1 and E1 primary rate
transmission links.
The MT9040 generates ST-BUS clock and framing
signals that are phase locked to either a 19.44 MHz,
2.048 MHz, 1.544 MHz, or 8 kHz input reference.
The MT9040 is compliant with AT&T TR62411 and
Bellcore GR-1244-CORE, Stratum 4; and ETSI ETS
300 011. It will meet the jitter/wander tolerance, jitter
transfer, intrinsic jitter, frequency accuracy and capture
range for these specifications.
February 2009
Ordering Information
MT9040AN 48 Pin SSOP Tubes
MT9040ANR 48 Pin SSOP Tape & Reel
MT9040AN1 48 Pin SSOP* Tubes
MT9040ANR1 48 Pin SSOP* Tape & Reel
*Pb Free Matte Tin
-40°C to +85°C
MT9040
T1/E1 Synchronizer
Data Sheet
Figure 1 - Functional Block Diagram
IEEE
1149.1a
Feedback
Control State Machine
DPLL
Frequency
Select
MUX
Input
Impairment
Monitor
Output
Interface
Circuit
MS FS1 FS2
TCK
RST
VDD VSS
C1.5o
C19o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
OSCoOSCi
Master Clock
TDO
TDI
TMS
TRST
C6o
RSP
TSP
FLOCK LOCK
IM
REF
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
MT9040 Data Sheet
2
Zarlink Semiconductor Inc.
Change Summary
Changes from February 2005 Issue to February 2009 Issue.
Figure 2 - Pin Connections
Page Item Change
12 Lock Indicator Corrected the Lock Indicator description.
Pin Description
Pin # Name Description
1,10,
23,31
V
SS
Ground. 0 Volts. (Vss pads).
2
RST
Reset (Input). A logic low at this input resets the MT9040. To ensure proper operation, the
device must be reset after reference signal frequency changes and power-up. The RST pin
should be held low for a minimum of 300 ns. While the RST pin is low, all frame pulses except
RST and TSP and all clock outputs except C6o, C16o and C19o are at logic high. The RST,
TSP, C6o and C16o are at logic low during reset. The C19o is free-running during reset.
Following a reset, the input reference source and output clocks and frame pulses are phase
aligned as shown in Figure 9.
3,4,5,
38,43
IC Internal Connection. Leave open circuit.
6REFReference (Input). This is the input reference source (falling edge) used for synchronization.
One of four possible frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) may be used.
7,17
28,35
V
DD
Positive Supply Voltage. +3.3V
DC
nominal.
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
TRST
TDI
TDO
IC
IC
FS1
FS2
IC
IC
IC
MS
Vdd
IC
IC
NC
Vss
IC
IM
Vdd
RST
IC
IC
REF
Vdd
OSCo
OSCi
Vss
F16o
TSP
F8o
C1.5o
C2o
C4o
C19o
48
TMS
V
SS
21
27
C6o
FLOCK
22
26
Vss
23
25
C8o
IC
24
C16o
MT9040AN
TCK
RSP
F0o
IC
Vdd
LOCK
MT9040 Data Sheet
3
Zarlink Semiconductor Inc.
8OSCoOscillator Master Clock (CMOS Output). For crystal operation, a 20 MHz crystal is
connected from this pin to OSCi, see Figure 6. Not suitable for driving other devices. For clock
oscillator operation, this pin is left unconnected, see Figure 5.
9OSCiOscillator Master Clock (CMOS Input). For crystal operation, a 20 MHz crystal is
connected from this pin to OSCo, see Figure 6. For clock oscillator operation, this pin is
connected to a clock source, see Figure 5.
11 F16o
Frame Pulse ST-BUS 8.192 Mb/s (CMOS Output). This is an 8 kHz 61 ns active low framing
pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUS
operation at 8.192 Mb/s. See Figure 11.
12 F0o
Frame Pulse ST-BUS 2.048 Mb/s (CMOS Output). This is an 8 kHz 244 ns active low
framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-
BUS operation at 2.048 Mb/s and 4.096 Mb/s. See Figure 11.
13 RSP Receive Sync Pulse (CMOS Output). This is an 8 kHz 488 ns active high framing pulse,
which marks the beginning of an ST-BUS frame. This is typically used for connection to the
Siemens MUNICH-32 device. See Figure 12.
14 TSP Transmit Sync Pulse (CMOS Output). This is an 8 kHz 488 ns active high framing pulse,
which marks the beginning of an ST-BUS frame. This is typically used for connection to the
Siemens MUNICH-32 device. See Figure 12.
15 F8o Frame Pulse (CMOS Output). This is an 8 kHz 122 ns active high framing pulse, which
marks the beginning of a frame. See Figure 11.
16 C1.5o Clock 1.544 MHz (CMOS Output). This output is used in T1 applications.
18 LOCK Lock Indicator (CMOS Output). This output goes high when the PLL is frequency locked to
the input reference.
19 C2o Clock 2.048 MHz (CMOS Output). This output is used for ST-BUS operation at 2.048 Mb/s.
20 C4o
Clock 4.096 MHz (CMOS Output). This output is used for ST-BUS operation at 2.048 Mb/s
and 4.096 Mb/s.
21 C19o Clock 19.44 MHz (CMOS Output). This output is used in OC3/STS3 applications.
22 FLOCK Fast Lock Mode (Input). Set high to allow the PLL to quickly lock to the input reference (less
than 500 ms locking time).
24 IC Internal Connection. Tie low for normal operation.
25 C8o Clock 8.192 MHz (CMOS Output). This output is used for ST-BUS operation at 8.192 Mb/s.
26 C16o
Clock 16.384 MHz (CMOS Output). This output is used for ST-BUS operation with a
16.384 MHz clock.
27 C6o Clock 6.312 Mhz (CMOS Output). This output is used for DS2 applications.
29 IM Impairment Monitor (CMOS Output). A logic high on this pin indicates that the Input
Impairment Monitor has automatically put the device into Freerun Mode.
30 IC Internal Connection. Tie high for normal operation.
32 NC No Connection. Leave open circuit.
33,34,
42
IC Internal Connection. Tie low for normal operation.
Pin Description (continued)
Pin # Name Description

MT9040ANR1

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Clock Generators & Support Products Pb Free T1/E1 SYNCHRONIZER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet