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MT9040ANR1

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
MT9040 Data Sheet
4
Zarlink Semiconductor Inc.
Functional Description
The MT9040 is a T1/E1 Trunk Synchronizer, providing timing (clock) and synchronization (frame) signals to
interface circuits for T1 and E1 Primary Rate Digital Transmission links. Figure 1 is a functional block diagram which
is described in the following sections.
Frequency Select MUX Circuit
The MT9040 operates on the falling edge of the reference. It operates with one of four possible input reference
frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz). The frequency select inputs (FS1 and FS2) determine
which of the four frequencies may be used at the reference input. A reset (RST
) must be performed after every
frequency select input change. See Table 1.
Table 1 - Input Frequency Selection
Digital Phase Lock Loop (DPLL)
As shown in Figure 3, the DPLL of the MT9040 consists of a Phase Detector, Loop Filter, Digitally Controlled
Oscillator and a Control Circuit.
36 MS Mode/Control Select (Input). This input determines the state (Normal or Freerun) of
operation. The logic level at this input is gated in by the rising edge of F8o. See Table 2.
37, 39 IC Internal Connection. Tie low for normal operation.
40 FS2 Frequency Select 2 (Input). This input, in conjunction with FS1, selects which of four possible
frequencies (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz) may be input to the REF input. See
Table 1.
41 FS1 Frequency Select 1 (Input). See pin description for FS2.
44 TDO Test Serial Data Out (CMOS Output). JTAG serial data is output on this pin on the falling
edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled.
45 TDI Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this pin.
This pin is internally pulled up to V
DD
.
46 TRST
Test Reset (Input). Asynchronously initializes the JTAG TAP controller by putting it in the
Test-Logic-Reset state. If not used, this pin should be held low.
47 TCK Test Clock (Input). Provides the clock to the JTAG test logic.
48 TMS Test Mode Select (Input). JTAG signal that controls the state transitions of the TAP controller.
FS2 FS1 Input Frequency
0 0 19.44 MHz
01 8kHz
1 0 1.544 MHz
1 1 2.048 MHz
Pin Description (continued)
Pin # Name Description
MT9040 Data Sheet
5
Zarlink Semiconductor Inc.
Phase Detector - the Phase Detector compares the reference signal with the feedback signal from the Frequency
Select MUX circuit, and provides an error signal corresponding to the phase difference between the two. This error
signal is passed to the Loop Filter. The Frequency Select MUX allows the proper feedback signal to be externally
selected (e.g., 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz).
Figure 3 - DPLL Block Diagram
Loop Filter - the Loop Filter is similar to a first order low pass filter with a 1.9 Hz cutoff frequency for all four
reference frequency selections (8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz). This filter ensures that the network
jitter transfer requirements are met.
Control Circuit - the Control Circuit uses status and control information from the State Machine and the Input
Impairment Circuit to set the mode of the DPLL. The two possible modes are Normal and Freerun.
Digitally Controlled Oscillator (DCO) - the DCO receives the filtered signal from the Loop Filter, and based on its
value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on
the state of the MT9040.
In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the input reference
signal.
In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20 MHz source.
Lock Indicator - If the PLL is in frequency lock (frequency lock means the center frequency of the PLL is identical to
the line frequency), and the input phase offset is small, then the lock signal will be set high. For specific Lock
Indicator design recommendations, see the Applications - Lock Indicator section.
Output Interface Circuit
The output of the DCO (DPLL) is used by the Output Interface Circuit to provide the output signals shown in Figure
4. The Output Interface Circuit uses four Tapped Delay Lines followed by a T1 Divider Circuit, an E1 Divider Circuit,
and a DS2 Divider Circuit to generate the required output signals.
Four tapped delay lines are used to generate 16.384 MHz, 12.352 MHz, 12.624 MHz and 19.44 MHz signals.
The E1 Divider Circuit uses the 16.38 4MHz signal to generate four clock outputs and five frame pulse outputs. The
C8o, C4o
and C2o clocks are generated by simply dividing the C16o clock by two, four and eight respectively.
These outputs have a nominal 50% duty cycle.
The T1 Divider Circuit uses the 12.384 MHz signal to generate the C1.5o clock by dividing the internal C12 clock
by eight. This output has a nominal 50% duty cycle.
The DS2 Divider Circuit uses the 12.624 MHz signal to generate the clock output C6o. This output has a nominal
50% duty cycle.
Control
Circuit
State Select
from
Input Impairment Monitor
State Select
from
State Machine
Feedback Signal
from
Frequency Select MUX
DPLL Reference
to
Output Interface Circuit
Loop Filter
Digitally
Controlled
Oscillator
Phase
Detector
Reference
MT9040 Data Sheet
6
Zarlink Semiconductor Inc.
Figure 4 - Output Interface Circuit Block Diagram
The frame pulse outputs (F0o
, F8o, F16o, TSP, and RSP) are generated directly from the C16 clock.
The T1 and E1 signals are generated from a common DPLL signal. Consequently, all frame pulse and clock outputs
are locked to one another for all operating states, and are also locked to the input reference in Normal Mode. See
Figures 10,11 and 12.
All frame pulse and clock outputs have limited driving capability, and should be buffered when driving high
capacitance (e.g., 30 pF) loads.
Input Impairment Monitor
This circuit monitors the input signal to the DPLL for a complete loss of incoming signal, or a large frequency shift in
the incoming signal. If the input signal is outside the Impairment Monitor Capture Range the PLL automatically
changes from Normal Mode to Free Run Mode. See AC Electrical Characteristics - Performance for the Impairment
Monitor Capture Range. When the incoming signal returns to normal, the DPLL is returned to Normal Mode.
Master Clock
The MT9040 can use either a clock or crystal as the master timing source. For recommended master timing
circuits, see the Applications - Master Clock section.
Tapped
Delay
Line
From
DPLL
T1 Divider
E1 Divider
16 MHz
12 MHz
C1.5o
C2o
C4o
C8o
C16o
F0o
F8o
F16o
Tapped
Delay
Line
Tapped
Delay
Line
Tapped
Delay
Line
DS2 Divider
12 MHz
19 MHz
C6o
C19o
RSP
TSP
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

MT9040ANR1

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Manufacturer:
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Description:
Clock Generators & Support Products Pb Free T1/E1 SYNCHRONIZER
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