MT9040ANR1 Datasheet MT9040AN1, MT9040ANR1 | P7-P9

MT9040 Data Sheet

Zarlink Semiconductor Inc.

Control and Mode of Operation

The MT9040 has two possible modes of operation, Normal and Freerun. As shown in Table 2, the Mode/Control

Select pin MS selects the mode.

Normal Mode

Normal Mode is typically used when a slave clock source, synchronized to the network is required.

In Normal Mode, the MT9040 provides timing (C1.5o, C2o, C4o

, C8o, C16o and C19o) and frame synchronization

(F0o

, F8o, F16o, TSP and RSP) signals, which are synchronized to the reference input. The input reference signal

may have a nominal frequency of 8 kHz, 1.544 MHz, 2.048 MHz or 19.44 MHz.

From a reset condition, the MT9040 will take up to 30 seconds (see AC Electrical Characteristics) of input reference

signal to output signals which are synchronized (phase locked) to the reference input.

The reference frequencies are selected by the frequency control pins FS2 and FS1 as shown in Table 1.

Fast Lock Mode

Fast Lock Mode is a submode of Normal Mode, it is used to allow the MT9040 to lock to a reference more quickly

than Normal mode will allow. Typically, the PLL will lock to the incoming reference within 500 ms if the FLOCK pin is

set high.

Freerun Mode

Freerun Mode is typically used when a master clock source is required, or immediately following system power-up

before network synchronization is achieved.

In Freerun Mode, the MT9040 provides timing and synchronization signals which are based on the master clock

frequency (OSCi) only, and are not synchronized to the reference signal.

The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a

±32 ppm output clock

is required, the master clock must also be

±32 ppm. See Applications - Crystal and Clock Oscillator sections.

MT9040 Measures of Performance

The following are some synchronizer performance indicators and their corresponding definitions.

Intrinsic Jitter

Intrinsic jitter is the jitter produced by the synchronizing circuit and is measured at its output. It is measured by

applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Intrinsic jitter may

also be measured when the device is free running by measuring the output jitter of the device. Intrinsic jitter is

usually measured with various bandlimiting filters depending on the applicable standards. In the MT9040, the

intrinsic Jitter is limited to less than 0.02 UI on the 2.048 MHz and 1.544 MHz clocks.

MS Mode

0NORMAL

1 FREERUN

Table 2 - Operating Modes and States

MT9040 Data Sheet

Zarlink Semiconductor Inc.

Jitter Tolerance

Jitter tolerance is a measure of the ability of a PLL to operate properly (i.e., remain in lock and or regain lock in the

presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its reference. The applied

jitter magnitude and jitter frequency depends on the applicable standards.

Jitter Transfer

Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter

at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured

with various filters depending on the applicable standards.

For the MT9040, the jitter attenuation is determined by the 1.9 Hz low pass loop filter.

The MT9040 has twelve outputs with three possible input frequencies (except for 19.44 MHz, which is internally

divided to 8 KHz) for a total of 36 possible jitter transfer functions. Since all outputs are derived from the same

signal, the jitter transfer values for the four cases, 8 kHz to 8 kHz, 1.544 MHz to 1.544 MHz and 2.048 MHz to

2.048 MHz can be applied to all outputs.

It should be noted that 1 UI at 1.544 MHz is 644 ns, which is not equal to 1 UI at 2.048 MHz, which is 488 ns.

Consequently, a transfer value using different input and output frequencies must be calculated in common units

(e.g., seconds) as shown in the following example.

What is the T1 and E1 output jitter when the T1 input jitter is 20 UI (T1 UI Units) and the T1 to T1 jitter attenuation is

18 dB?

Using the above method, the jitter attenuation can be calculated for all combinations of inputs and outputs based on

the three jitter transfer functions provided.

Note that the resulting jitter transfer functions for all combinations of inputs (8 kHz, 1.544 MHz, 2.048 MHz) and

outputs (8 kHz, 1.544 MHz, 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz, 19.44 MHz) for a given input signal

(jitter frequency and jitter amplitude) are the same.

Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than for

large ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter

signals (e.g., 75% of the specified maximum jitter tolerance).

Frequency Accuracy

Frequency accuracy is defined as the absolute tolerance of an output clock signal when it is not locked to an

external reference, but is operating in a free running mode. For the MT9040, the Freerun accuracy is equal to the

Master Clock (OSCi) accuracy.

OutputT1 InputT1

A–

-------

⎝⎠

⎛⎞

×10=

OutputT1 20

18–

-------- -

⎝⎠

⎛⎞

×10 2.5UI T1()==

OutputE1 OutputT1

644ns()

488ns()

-------------------

3.3UI T1()=×=

OutputE1 OutputT1

1UIT1()

1UIE1()

----------------------

×=

MT9040 Data Sheet

Zarlink Semiconductor Inc.

Capture Range

Also referred to as pull-in range. This is the input frequency range over which the synchronizer must be able to pull

into synchronization. The MT9040 capture range is equal to

±230 ppm minus the accuracy of the master clock

(OSCi). For example, a 32 ppm master clock results in a capture range of 198 ppm.

Lock Range

This is the input frequency range over which the synchronizer must be able to maintain synchronization. The lock

range is equal to the capture range for the MT9040.

Phase Lock Time

This is the time it takes the synchronizer to phase lock to the input signal. Phase lock occurs when the input signal

and output signal are not changing in phase with respect to each other (not including jitter).

Lock time is very difficult to determine because it is affected by many factors which include:

• initial input to output phase difference

• initial input to output frequency difference

• synchronizer loop filter

Although a short lock time is desirable, it is not always possible to achieve due to other synchronizer requirements.

For instance, better jitter transfer performance is achieved with a lower frequency loop filter which increases lock

time. See AC Electrical Characteristics - Performance for Maximum Phase Lock Time.

MT9040 provides a fast lock pin (FLOCK), which, when set high enables the PLL to lock to an incoming reference

within approximately 500 ms.

MT9040 and Network Specifications

The MT9040 fully meets all applicable PLL requirements (intrinsic jitter, jitter/wander tolerance, jitter/wander

transfer, frequency accuracy and capture range for the following specifications.

1. Bellcore GR-1244-CORE June 1995 for Stratum 4

2. AT&T TR62411(DS1) December 1990 for Stratum 4

3. ANSI T1.101 (DS1) February 1994 for Stratum 4

4. ETSI 300 011 (E1) April 1992

5. TBR 4 November 1995

6. TBR 12 December 1993

7. TBR 13 January 1996

8. ITU-T I.431 March 1993

Applications

This section contains MT9040 application specific details for clock and crystal operation, reset operation, power

supply decoupling, and control operation.

Master Clock

The MT9040 can use either a clock or crystal as the master timing source.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P26

MT9040ANR1

Mfr. #:

Buy MT9040ANR1

Manufacturer:

Microchip / Microsemi

Description:

Clock Generators & Support Products Pb Free T1/E1 SYNCHRONIZER

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

MT9040ANR1

MT9040ANR1

Products related to this Datasheet