OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

M34C02-WDW6T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
M34C02
10/28
Figure 9. Write Mode Sequences in a Non Write-Protected Area
Write Operations
Following a Start condition the bus master sends
a Device Select Code with the RW
bit reset to 0.
The device acknowledges this, as shown in Figure
9., and waits for an address byte. The device re-
sponds to the address byte with an acknowledge
bit, and then waits for the data byte.
When the bus master generates a Stop condition
immediately after the Ack bit (in the “10
th
bit” time
slot), either at the end of a Byte Write or a Page
Write, the internal memory Write cycle is triggered.
A Stop condition at any other time slot does not
trigger the internal Write cycle.
During the internal Write cycle, Serial Data (SDA)
and Serial Clock (SCL) are ignored, and the de-
vice does not respond to any requests.
Byte Write
After the Device Select Code and the address
byte, the bus master sends one data byte. If the
addressed location is hardware write-protected,
the device replies to the data byte with NoAck, and
the location is not modified. If, instead, the ad-
dressed location is not Write-protected, the device
replies with Ack. The bus master terminates the
transfer by generating a Stop condition, as shown
in Figure 9..
Page Write
The Page Write mode allows up to 16 bytes to be
written in a single Write cycle, provided that they
are all located in the same page in the memory:
that is, the most significant memory address bits
are the same. If more bytes are sent than will fit up
to the end of the page, a condition known as ‘roll-
over’ occurs. This should be avoided, as data
starts to become overwritten in an implementation
dependent way.
The bus master sends from 1 to 16 bytes of data,
each of which is acknowledged by the device if
Write Control (WC
) is Low. If the addressed loca-
tion is hardware write-protected, the device replies
to the data byte with NoAck, and the locations are
not modified. After each byte is transferred, the in-
ternal byte address counter (the 4 least significant
address bits only) is incremented. The transfer is
terminated by the bus master generating a Stop
condition.
STOP
START
BYTE WRITE DEV SEL BYTE ADDR
DATA IN
START
PAGE WRITE DEV SEL BYTE ADDR
DATA IN 1 DATA IN 2
AI01941
STOP
DATA IN N
ACK ACK
ACK
R/W
ACK
ACK ACK
R/W
ACK ACK
11/28
M34C02
Figure 10. Write Cycle Polling Flowchart using ACK
Minimizing System Delays by Polling On ACK
During the internal Write cycle, the device discon-
nects itself from the bus, and writes a copy of the
data from its internal latches to the memory cells.
The maximum Write time (t
w
) is shown in Table
17. and Table 18., but the typical time is shorter.
To make use of this, a polling sequence can be
used by the bus master.
The sequence, as shown in Figure 10., is:
– Initial condition: a Write cycle is in progress.
– Step 1: the bus master issues a Start condition
followed by a Device Select Code (the first
byte of the new instruction).
– Step 2: if the device is busy with the internal
Write cycle, no Ack will be returned and the
bus master goes back to Step 1. If the device
has terminated the internal Write cycle, it
responds with an Ack, indicating that the
device is ready to receive the second part of
the instruction (the first byte of this instruction
having been sent during Step 1).
WRITE Cycle
in Progress
AI01847C
Next
Operation is
Addressing the
Memory
START Condition
DEVICE SELECT
with RW = 0
ACK
Returned
YES
NO
YESNO
ReSTART
STOP
DATA for the
WRITE Operation
DEVICE SELECT
with RW = 1
Send Address
and Receive ACK
First byte of instruction
with RW = 0 already
decoded by the device
YESNO
START
Condition
Continue the
WRITE Operation
Continue the
Random READ Operation
M34C02
12/28
Figure 11. Read Mode Sequences
Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1
st
and 3
rd
bytes) must be identical.
Read Operations
Read operations are performed independently of
whether hardware or software protection has been
set.
The device has an internal address counter which
is incremented each time a byte is read.
Random Address Read
A dummy Write is first performed to load the ad-
dress into this address counter (as shown in Fig-
ure 11.) but without sending a Stop condition.
Then, the bus master sends another Start condi-
tion, and repeats the Device Select Code, with the
RW
bit set to 1. The device acknowledges this,
and outputs the contents of the addressed byte.
The bus master must not acknowledge the byte,
and terminates the transfer with a Stop condition.
Current Address Read
For the Current Address Read operation, following
a Start condition, the bus master only sends a De-
vice Select Code with the RW
bit set to 1. The de-
vice acknowledges this, and outputs the byte
addressed by the internal address counter. The
counter is then incremented. The bus master ter-
minates the transfer with a Stop condition, as
shown in Figure 11., without acknowledging the
byte.
START
DEV SEL * BYTE ADDR
START
DEV SEL DATA OUT 1
AI01942
DATA OUT N
STOP
START
CURRENT
ADDRESS
READ
DEV SEL DATA OUT
RANDOM
ADDRESS
READ
STOP
START
DEV SEL * DATA OUT
SEQUENTIAL
CURRENT
READ
STOP
DATA OUT N
START
DEV SEL * BYTE ADDR
SEQUENTIAL
RANDOM
READ
START
DEV SEL * DATA OUT 1
STOP
ACK
R/W
NO ACK
ACK
R/W
ACK ACK
R/W
ACK ACK
ACK NO ACK
R/W
NO ACK
ACK ACK
R/W
ACK ACK
R/W
ACK NO ACK
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

M34C02-WDW6T

Mfr. #:
Buy M34C02-WDW6T
Manufacturer:
STMicroelectronics
Description:
EEPROM 5.5V 2K (256x8)
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet